From e9de95d7e0629c40b5ceb56c07de319bedd3339f Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 9 Jan 2018 14:33:51 -0800 Subject: gpu: nvgpu: use chip specific zbc_c/z format reg Use chip specific gpcs_swdx_dss_zbc_c_format_reg and gpcs_swdx_dss_zbc_z_format_reg. These registers are different for gv11b/gv100 from gp10b/gp106. Change-Id: I9e209c878a11edc986ba4304ff60fcccbb5087aa Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1635091 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 9156d9b8..f19832b9 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -281,6 +281,10 @@ static const struct gpu_ops gv11b_ops = { .detect_sm_arch = gr_gv11b_detect_sm_arch, .add_zbc_color = gr_gp10b_add_zbc_color, .add_zbc_depth = gr_gp10b_add_zbc_depth, + .get_gpcs_swdx_dss_zbc_c_format_reg = + gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg, + .get_gpcs_swdx_dss_zbc_z_format_reg = + gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg, .zbc_set_table = gk20a_gr_zbc_set_table, .zbc_query_table = gr_gk20a_query_zbc, .pmu_save_zbc = gk20a_pmu_save_zbc, -- cgit v1.2.2