From 55a5c57bc1fd532cc6d041fdfb70d90286894b35 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 7 Apr 2016 16:57:18 -0700 Subject: gpu: nvgpu: gv11b: added initial source code Bug 1735757 Change-Id: Iea7488551a437afa0dfc005c87ad1b9ab9673b6c Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1122123 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 45 +++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 drivers/gpu/nvgpu/gv11b/hal_gv11b.c (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c new file mode 100644 index 00000000..0debe7ce --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -0,0 +1,45 @@ +/* + * GV11B Tegra HAL interface + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#include + +#include "gk20a/gk20a.h" + +#include "gv11b/gr_gv11b.h" +#include "gv11b/mc_gv11b.h" + +#include "gm20b/gr_gm20b.h" + +int gv11b_init_hal(struct gk20a *g) +{ + struct gpu_ops *gops = &g->ops; + struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + + gv11b_init_mc(gops); + gv11b_init_gr(gops); + gops->name = "gv11b"; + + c->twod_class = FERMI_TWOD_A; + c->threed_class = VOLTA_A; + c->compute_class = VOLTA_COMPUTE_A; + c->gpfifo_class = VOLTA_CHANNEL_GPFIFO_A; + c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; + c->dma_copy_class = VOLTA_DMA_COPY_A; + + return 0; +} -- cgit v1.2.2 From c84ddceda648d6e47828115654ca7745010ec09f Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 14 Apr 2016 13:01:58 -0700 Subject: gpu: nvgpu: gv11b: sm priv reg related changes Included all basic ops for gv11b and updated sm related functions to include new priv register addresses. Bug 1735757 Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1126961 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 0debe7ce..a30e3263 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -22,6 +22,14 @@ #include "gv11b/gr_gv11b.h" #include "gv11b/mc_gv11b.h" +#include "gv11b/ltc_gv11b.h" +#include "gv11b/fecs_trace_gv11b.h" +#include "gv11b/gv11b.h" +#include "gv11b/ce2_gv11b.h" +#include "gv11b/gr_ctx_gv11b.h" +#include "gv11b/mm_gv11b.h" +#include "gv11b/pmu_gv11b.h" +#include "gv11b/therm_gv11b.h" #include "gm20b/gr_gm20b.h" @@ -30,9 +38,22 @@ int gv11b_init_hal(struct gk20a *g) struct gpu_ops *gops = &g->ops; struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + /* boot in non-secure modes for time beeing */ + gops->privsecurity = 0; + gops->securegpccs = 0; + gv11b_init_mc(gops); + gv11b_init_ltc(gops); gv11b_init_gr(gops); + gv11b_init_fecs_trace_ops(gops); + gv11b_init_ce2(gops); + gv11b_init_mm(gops); + gv11b_init_gr_ctx(gops); + gv11b_init_pmu_ops(gops); + gk20a_init_debug_ops(gops); + gv11b_init_therm_ops(gops); gops->name = "gv11b"; + gops->chip_init_gpu_characteristics = gv11b_init_gpu_characteristics; c->twod_class = FERMI_TWOD_A; c->threed_class = VOLTA_A; -- cgit v1.2.2 From 66f64c86a838bb9bfec049e3676debd8998e8b08 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Mon, 18 Apr 2016 09:36:13 -0700 Subject: gpu: nvgpu: gv11b: fix sparse warnings Fixed following sparse warnings: drivers/gpu/nvgpu/gv11b/gv11b.c:21:5: warning: symbol 'gv11b_init_gpu_characteristics' was not declared. Should it be static? drivers/gpu/nvgpu/gv11b/hal_gv11b.c:36:5: warning: symbol 'gv11b_init_hal' was not declared. Should it be static? drivers/gpu/nvgpu/gv11b/gr_gv11b.c:766:5: warning: symbol 'gr_gv11b_alloc_buffer' was not declared. Should it be static? Bug 200088648 Change-Id: I327f9d69bf1853727d74d2c125cfab54c2f0e5b0 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1128299 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index a30e3263..e340c97e 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -20,6 +20,7 @@ #include "gk20a/gk20a.h" +#include "gv11b/hal_gv11b.h" #include "gv11b/gr_gv11b.h" #include "gv11b/mc_gv11b.h" #include "gv11b/ltc_gv11b.h" -- cgit v1.2.2 From 6f24a7666045b25072282d4c29ff190b7af33e59 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Thu, 2 Jun 2016 09:44:13 +0530 Subject: gpu: nvgpu: Add multiple engine and runlist support This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt support for Volta GPU series 5) Removed hard coded engine_id logic and made generic way 6) Code cleanup for readability JIRA DNVGPU-26 Change-Id: Ief3b586ff3d9f492f0277243b2a94952bab48786 Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1156023 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index e340c97e..876b5748 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -26,7 +26,7 @@ #include "gv11b/ltc_gv11b.h" #include "gv11b/fecs_trace_gv11b.h" #include "gv11b/gv11b.h" -#include "gv11b/ce2_gv11b.h" +#include "gv11b/ce_gv11b.h" #include "gv11b/gr_ctx_gv11b.h" #include "gv11b/mm_gv11b.h" #include "gv11b/pmu_gv11b.h" @@ -47,7 +47,7 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_ltc(gops); gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); - gv11b_init_ce2(gops); + gv11b_init_ce(gops); gv11b_init_mm(gops); gv11b_init_gr_ctx(gops); gv11b_init_pmu_ops(gops); -- cgit v1.2.2 From 32fe739f68e6307062a8a3f535be41208c97766d Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 7 Jul 2016 13:47:48 -0700 Subject: gpu: nvgpu: gv11b: updated hal and gpu_ops Added init_fb, init_fifo and get_litter_values. Also initialized read_ptimer Bug 1735760 Change-Id: Ia1665d60392e9cc58db4cc3f292597aeaea0c718 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1177174 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu Reviewed-by: Adeel Raza --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 88 ++++++++++++++++++++++++++++++++++++- 1 file changed, 87 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 876b5748..33b0d955 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -31,14 +31,96 @@ #include "gv11b/mm_gv11b.h" #include "gv11b/pmu_gv11b.h" #include "gv11b/therm_gv11b.h" +#include "gv11b/fb_gv11b.h" +#include "gv11b/fifo_gv11b.h" +#include "gv11b/hw_proj_gv11b.h" #include "gm20b/gr_gm20b.h" +static struct gpu_ops gv11b_ops; + +static int gv11b_get_litter_value(struct gk20a *g, + enum nvgpu_litter_value value) +{ + int ret = EINVAL; + switch (value) { + case GPU_LIT_NUM_GPCS: + ret = proj_scal_litter_num_gpcs_v(); + break; + case GPU_LIT_NUM_PES_PER_GPC: + ret = proj_scal_litter_num_pes_per_gpc_v(); + break; + case GPU_LIT_NUM_ZCULL_BANKS: + ret = proj_scal_litter_num_zcull_banks_v(); + break; + case GPU_LIT_NUM_TPC_PER_GPC: + ret = proj_scal_litter_num_tpc_per_gpc_v(); + break; + case GPU_LIT_NUM_FBPS: + ret = proj_scal_litter_num_fbps_v(); + break; + case GPU_LIT_GPC_BASE: + ret = proj_gpc_base_v(); + break; + case GPU_LIT_GPC_STRIDE: + ret = proj_gpc_stride_v(); + break; + case GPU_LIT_GPC_SHARED_BASE: + ret = proj_gpc_shared_base_v(); + break; + case GPU_LIT_TPC_IN_GPC_BASE: + ret = proj_tpc_in_gpc_base_v(); + break; + case GPU_LIT_TPC_IN_GPC_STRIDE: + ret = proj_tpc_in_gpc_stride_v(); + break; + case GPU_LIT_TPC_IN_GPC_SHARED_BASE: + ret = proj_tpc_in_gpc_shared_base_v(); + break; + case GPU_LIT_PPC_IN_GPC_STRIDE: + ret = proj_ppc_in_gpc_stride_v(); + break; + case GPU_LIT_ROP_BASE: + ret = proj_rop_base_v(); + break; + case GPU_LIT_ROP_STRIDE: + ret = proj_rop_stride_v(); + break; + case GPU_LIT_ROP_SHARED_BASE: + ret = proj_rop_shared_base_v(); + break; + case GPU_LIT_HOST_NUM_ENGINES: + ret = proj_host_num_engines_v(); + break; + case GPU_LIT_HOST_NUM_PBDMA: + ret = proj_host_num_pbdma_v(); + break; + case GPU_LIT_LTC_STRIDE: + ret = proj_ltc_stride_v(); + break; + case GPU_LIT_LTS_STRIDE: + ret = proj_lts_stride_v(); + break; + case GPU_LIT_NUM_FBPAS: + ret = proj_scal_litter_num_fbpas_v(); + break; + case GPU_LIT_FBPA_STRIDE: + ret = proj_fbpa_stride_v(); + break; + default: + break; + } + + return ret; +} + int gv11b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + *gops = gv11b_ops; + /* boot in non-secure modes for time beeing */ gops->privsecurity = 0; gops->securegpccs = 0; @@ -47,14 +129,18 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_ltc(gops); gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); + gv11b_init_fb(gops); + gv11b_init_fifo(gops); gv11b_init_ce(gops); gv11b_init_mm(gops); gv11b_init_gr_ctx(gops); gv11b_init_pmu_ops(gops); - gk20a_init_debug_ops(gops); + gk20a_init_debug_ops(gops); gv11b_init_therm_ops(gops); gops->name = "gv11b"; gops->chip_init_gpu_characteristics = gv11b_init_gpu_characteristics; + gops->get_litter_value = gv11b_get_litter_value; + gops->read_ptimer = gk20a_read_ptimer; c->twod_class = FERMI_TWOD_A; c->threed_class = VOLTA_A; -- cgit v1.2.2 From 0b05d33d8af2dc602ffc78de4c16432b083ec80f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 24 Aug 2016 09:18:14 -0700 Subject: gpu: nvgpu: gv11b : add mm and tsg init Bug 1735760 Change-Id: I6b33b38ed555759a57ad170e7f75839df51da228 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1207273 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 33b0d955..af87636a 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -132,11 +132,12 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_fb(gops); gv11b_init_fifo(gops); gv11b_init_ce(gops); - gv11b_init_mm(gops); gv11b_init_gr_ctx(gops); + gv11b_init_mm(gops); gv11b_init_pmu_ops(gops); gk20a_init_debug_ops(gops); gv11b_init_therm_ops(gops); + gk20a_init_tsg_ops(gops); gops->name = "gv11b"; gops->chip_init_gpu_characteristics = gv11b_init_gpu_characteristics; gops->get_litter_value = gv11b_get_litter_value; -- cgit v1.2.2 From e1bcaa33abd46fd7e2b66ad09a02f7f30d6a0dfe Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 28 Oct 2016 17:11:21 -0700 Subject: gpu: nvgpu: gv11b: add dbg_session_ops JIRA GV11B-21 Change-Id: Ib9c099fb0f9cf910bd5abfc9fd6010803b52c9f8 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1244768 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index af87636a..a11d6a71 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -36,6 +36,7 @@ #include "gv11b/hw_proj_gv11b.h" #include "gm20b/gr_gm20b.h" +#include "gk20a/dbg_gpu_gk20a.h" static struct gpu_ops gv11b_ops; @@ -136,6 +137,7 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_mm(gops); gv11b_init_pmu_ops(gops); gk20a_init_debug_ops(gops); + gk20a_init_dbg_session_ops(gops); gv11b_init_therm_ops(gops); gk20a_init_tsg_ops(gops); gops->name = "gv11b"; -- cgit v1.2.2 From 7b67abb2edb606b9ad0d0ecf0d94a333770974b1 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 16 Nov 2016 09:33:43 -0800 Subject: gpu: nvgpu: gv11b: support for new littler values Add support for new litter values: GPU_LIT_NUM_SUBCTX GPU_LIT_NUM_SM_PER_TPC Also updated get_litter_value api to use int instead of enum type. JIRA GV11B-21 Change-Id: Ide06245d03743e2d757d27d045701beb25b6707b Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1254857 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index a11d6a71..3124f540 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -17,7 +17,7 @@ #include #include - +#include #include "gk20a/gk20a.h" #include "gv11b/hal_gv11b.h" @@ -40,8 +40,7 @@ static struct gpu_ops gv11b_ops; -static int gv11b_get_litter_value(struct gk20a *g, - enum nvgpu_litter_value value) +static int gv11b_get_litter_value(struct gk20a *g, int value) { int ret = EINVAL; switch (value) { @@ -57,6 +56,9 @@ static int gv11b_get_litter_value(struct gk20a *g, case GPU_LIT_NUM_TPC_PER_GPC: ret = proj_scal_litter_num_tpc_per_gpc_v(); break; + case GPU_LIT_NUM_SM_PER_TPC: + ret = proj_scal_litter_num_sm_per_tpc_v(); + break; case GPU_LIT_NUM_FBPS: ret = proj_scal_litter_num_fbps_v(); break; @@ -108,6 +110,9 @@ static int gv11b_get_litter_value(struct gk20a *g, case GPU_LIT_FBPA_STRIDE: ret = proj_fbpa_stride_v(); break; + case GPU_LIT_NUM_SUBCTX: + ret = proj_litter_num_subctx_v(); + break; default: break; } -- cgit v1.2.2 From 35969806d2c763d4a5662ba6a9233a63aa00352d Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 2 Dec 2016 10:45:09 -0800 Subject: gpu: nvgpu: gv11b: add clock gating prod settings JIRA GV11B-15 Change-Id: I38d8cbda33f9c4e8b44ca227cd5ea5fef346bfbd Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1266705 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 54 +++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 3124f540..ccaa570c 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -34,12 +34,66 @@ #include "gv11b/fb_gv11b.h" #include "gv11b/fifo_gv11b.h" #include "gv11b/hw_proj_gv11b.h" +#include "gv11b/gv11b_gating_reglist.h" #include "gm20b/gr_gm20b.h" #include "gk20a/dbg_gpu_gk20a.h" static struct gpu_ops gv11b_ops; +static struct gpu_ops gv11b_ops = { + .clock_gating = { + .slcg_bus_load_gating_prod = + gv11b_slcg_bus_load_gating_prod, + .slcg_ce2_load_gating_prod = + gv11b_slcg_ce2_load_gating_prod, + .slcg_chiplet_load_gating_prod = + gv11b_slcg_chiplet_load_gating_prod, + .slcg_ctxsw_firmware_load_gating_prod = + gv11b_slcg_ctxsw_firmware_load_gating_prod, + .slcg_fb_load_gating_prod = + gv11b_slcg_fb_load_gating_prod, + .slcg_fifo_load_gating_prod = + gv11b_slcg_fifo_load_gating_prod, + .slcg_gr_load_gating_prod = + gr_gv11b_slcg_gr_load_gating_prod, + .slcg_ltc_load_gating_prod = + ltc_gv11b_slcg_ltc_load_gating_prod, + .slcg_perf_load_gating_prod = + gv11b_slcg_perf_load_gating_prod, + .slcg_priring_load_gating_prod = + gv11b_slcg_priring_load_gating_prod, + .slcg_pmu_load_gating_prod = + gv11b_slcg_pmu_load_gating_prod, + .slcg_therm_load_gating_prod = + gv11b_slcg_therm_load_gating_prod, + .slcg_xbar_load_gating_prod = + gv11b_slcg_xbar_load_gating_prod, + .blcg_bus_load_gating_prod = + gv11b_blcg_bus_load_gating_prod, + .blcg_ce_load_gating_prod = + gv11b_blcg_ce_load_gating_prod, + .blcg_ctxsw_firmware_load_gating_prod = + gv11b_blcg_ctxsw_firmware_load_gating_prod, + .blcg_fb_load_gating_prod = + gv11b_blcg_fb_load_gating_prod, + .blcg_fifo_load_gating_prod = + gv11b_blcg_fifo_load_gating_prod, + .blcg_gr_load_gating_prod = + gv11b_blcg_gr_load_gating_prod, + .blcg_ltc_load_gating_prod = + gv11b_blcg_ltc_load_gating_prod, + .blcg_pwr_csb_load_gating_prod = + gv11b_blcg_pwr_csb_load_gating_prod, + .blcg_pmu_load_gating_prod = + gv11b_blcg_pmu_load_gating_prod, + .blcg_xbar_load_gating_prod = + gv11b_blcg_xbar_load_gating_prod, + .pg_gr_load_gating_prod = + gr_gv11b_pg_gr_load_gating_prod, + } +}; + static int gv11b_get_litter_value(struct gk20a *g, int value) { int ret = EINVAL; -- cgit v1.2.2 From 4b09997772f406d16945016ff4581c7c992faeab Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 12 Jan 2017 13:01:36 -0800 Subject: nvgpu: gpu: HW header update for Volta Similar HW header update as has been done for all the other chips. HW header files are located under: drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/ And can be included like so: #include Bug 1799159 Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1284433 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 38 +++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index ccaa570c..07f386e8 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -1,7 +1,7 @@ /* * GV11B Tegra HAL interface * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,26 +18,28 @@ #include #include -#include "gk20a/gk20a.h" -#include "gv11b/hal_gv11b.h" -#include "gv11b/gr_gv11b.h" -#include "gv11b/mc_gv11b.h" -#include "gv11b/ltc_gv11b.h" -#include "gv11b/fecs_trace_gv11b.h" -#include "gv11b/gv11b.h" -#include "gv11b/ce_gv11b.h" -#include "gv11b/gr_ctx_gv11b.h" -#include "gv11b/mm_gv11b.h" -#include "gv11b/pmu_gv11b.h" -#include "gv11b/therm_gv11b.h" -#include "gv11b/fb_gv11b.h" -#include "gv11b/fifo_gv11b.h" -#include "gv11b/hw_proj_gv11b.h" -#include "gv11b/gv11b_gating_reglist.h" +#include "gk20a/gk20a.h" +#include "gk20a/dbg_gpu_gk20a.h" #include "gm20b/gr_gm20b.h" -#include "gk20a/dbg_gpu_gk20a.h" + +#include "hal_gv11b.h" +#include "gr_gv11b.h" +#include "mc_gv11b.h" +#include "ltc_gv11b.h" +#include "fecs_trace_gv11b.h" +#include "gv11b.h" +#include "ce_gv11b.h" +#include "gr_ctx_gv11b.h" +#include "mm_gv11b.h" +#include "pmu_gv11b.h" +#include "therm_gv11b.h" +#include "fb_gv11b.h" +#include "fifo_gv11b.h" +#include "gv11b_gating_reglist.h" + +#include static struct gpu_ops gv11b_ops; -- cgit v1.2.2 From 30e1647ddf5b4b272c63843e91d4c4b41529bd75 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 27 Jan 2017 10:59:47 -0800 Subject: gpu: nvgpu: gv11b: add regops whitelists Add regops whitelists for gv11b. JIRA GV11B-35 Change-Id: I0ff5172c5b693250efb0523106632b3746383dcb Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1295401 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 07f386e8..8b10245e 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -38,6 +38,7 @@ #include "fb_gv11b.h" #include "fifo_gv11b.h" #include "gv11b_gating_reglist.h" +#include "regops_gv11b.h" #include @@ -199,6 +200,7 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_pmu_ops(gops); gk20a_init_debug_ops(gops); gk20a_init_dbg_session_ops(gops); + gv11b_init_regops(gops); gv11b_init_therm_ops(gops); gk20a_init_tsg_ops(gops); gops->name = "gv11b"; -- cgit v1.2.2 From 207e2ac7d12e62df476f4828136a4c15e156f8a6 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 22 Feb 2017 10:04:31 -0800 Subject: gpu: nvgpu: gv11b: reading max veid number To get maximum number of subctx, sw should read NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT instead of LITTER_NUM_SUBCTX. JIRA GV11B-72 Change-Id: I4d675ba49d8a600da77e7b60da449d9e5ba48971 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1309591 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seema Khowala GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 8b10245e..133a1e8d 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -167,9 +167,6 @@ static int gv11b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_FBPA_STRIDE: ret = proj_fbpa_stride_v(); break; - case GPU_LIT_NUM_SUBCTX: - ret = proj_litter_num_subctx_v(); - break; default: break; } -- cgit v1.2.2 From d409d7ebc136470906b861f3bebb7da63e1557e6 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 17 Mar 2017 13:47:54 -0700 Subject: gpu: nvgpu: Add bus HAL Add bus HAL and separate bus related functions from mm_gv11b: timer access. Change-Id: I311f258857238233103688fb653d27e4e79005a4 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1323354 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 133a1e8d..1b580558 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -21,6 +21,7 @@ #include "gk20a/gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" +#include "gk20a/bus_gk20a.h" #include "gm20b/gr_gm20b.h" @@ -185,6 +186,7 @@ int gv11b_init_hal(struct gk20a *g) gops->privsecurity = 0; gops->securegpccs = 0; + gk20a_init_bus(gops); gv11b_init_mc(gops); gv11b_init_ltc(gops); gv11b_init_gr(gops); @@ -203,7 +205,6 @@ int gv11b_init_hal(struct gk20a *g) gops->name = "gv11b"; gops->chip_init_gpu_characteristics = gv11b_init_gpu_characteristics; gops->get_litter_value = gv11b_get_litter_value; - gops->read_ptimer = gk20a_read_ptimer; c->twod_class = FERMI_TWOD_A; c->threed_class = VOLTA_A; -- cgit v1.2.2 From 173cf315ad43267a22a5c3265fd65960b28fcf68 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 23 Mar 2017 15:49:58 -0700 Subject: gpu: nvgpu: gv11b: hal should use gv11b_init_bus gk20a_init_bus should not be used for gv11b hal init as bar1_bind is not supported. Change-Id: I59b6e991b12d8355b1f54ae3eaf78dc94ca6d767 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1327171 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 1b580558..ef09fc68 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -26,6 +26,7 @@ #include "gm20b/gr_gm20b.h" #include "hal_gv11b.h" +#include "bus_gv11b.h" #include "gr_gv11b.h" #include "mc_gv11b.h" #include "ltc_gv11b.h" @@ -186,7 +187,7 @@ int gv11b_init_hal(struct gk20a *g) gops->privsecurity = 0; gops->securegpccs = 0; - gk20a_init_bus(gops); + gv11b_init_bus(gops); gv11b_init_mc(gops); gv11b_init_ltc(gops); gv11b_init_gr(gops); -- cgit v1.2.2 From 9773dbf905acd7dbb7ebfbbdfae529ff6f9f8ab8 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 24 Mar 2017 10:55:21 -0700 Subject: gpu: nvgpu: Remove unnecessary use of dev_name() Move the name field from struct gpu_ops up to struct gk20a. The field is not a function op, so it doesn't belong in gpu_ops. Replace all uses of dev_name() with use of g->name when possible. JIRA NVGPU-16 Change-Id: I053aeb256f591af2ea9ef5094a20e33a395cdd33 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1328535 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index ef09fc68..32fd52d6 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -203,7 +203,7 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_regops(gops); gv11b_init_therm_ops(gops); gk20a_init_tsg_ops(gops); - gops->name = "gv11b"; + g->name = "gv11b"; gops->chip_init_gpu_characteristics = gv11b_init_gpu_characteristics; gops->get_litter_value = gv11b_get_litter_value; -- cgit v1.2.2 From 1c1b01d067c62e2f3bd102503131c8070291a5fc Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 18 Apr 2017 14:24:25 -0700 Subject: gpu: nvgpu: gv11b: init css ops Bug 1870532 Change-Id: Ib8d61e92ad825b9ae5345f62ed2df343b50231b0 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1464994 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 32fd52d6..220d646b 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -20,6 +20,7 @@ #include #include "gk20a/gk20a.h" +#include "gk20a/css_gr_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/bus_gk20a.h" @@ -203,6 +204,9 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_regops(gops); gv11b_init_therm_ops(gops); gk20a_init_tsg_ops(gops); +#if defined(CONFIG_GK20A_CYCLE_STATS) + gk20a_init_css_ops(gops); +#endif g->name = "gv11b"; gops->chip_init_gpu_characteristics = gv11b_init_gpu_characteristics; gops->get_litter_value = gv11b_get_litter_value; -- cgit v1.2.2 From e1c27d4e84d518bef88305d1ca848deb07433677 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 14 Apr 2017 16:15:50 -0700 Subject: gpu: nvgpu: gv11b: Use new clk HAL Use the new clk HAL to request clock rate instead of direct calls to Clock Framework. This cuts one direct dependency to Linux APIs. Also change the HAL to not clear clk ops after they've been initialized. JIRA NVGPU-16 Change-Id: I1ab3eac8268f1f3f3305d49782c6a0eb57c6d617 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1463536 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 220d646b..7e2c35dc 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -182,7 +182,7 @@ int gv11b_init_hal(struct gk20a *g) struct gpu_ops *gops = &g->ops; struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; - *gops = gv11b_ops; + gops->clock_gating = gv11b_ops.clock_gating; /* boot in non-secure modes for time beeing */ gops->privsecurity = 0; -- cgit v1.2.2 From 2266270e2a2dc34c20f25f5cf256662e9747c4ac Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Tue, 2 May 2017 21:18:34 +0530 Subject: gpu: nvgpu: init interface layer support for PMU falcon Change-Id: Iadd72196ed7df7384b1ecdc06ecd98828061fd3e Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1473685 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 7e2c35dc..de14f1dd 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -23,6 +23,7 @@ #include "gk20a/css_gr_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/bus_gk20a.h" +#include "gk20a/flcn_gk20a.h" #include "gm20b/gr_gm20b.h" @@ -198,6 +199,7 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_ce(gops); gv11b_init_gr_ctx(gops); gv11b_init_mm(gops); + gk20a_falcon_init_hal(gops); gv11b_init_pmu_ops(gops); gk20a_init_debug_ops(gops); gk20a_init_dbg_session_ops(gops); -- cgit v1.2.2 From b7af57e41b3b0b6e84bba07fbe371a77ee4eecb6 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 20 Apr 2017 16:44:36 -0700 Subject: gpu: nvgpu: gv11b: init priv ring HAL Initialize priv ring HAL. Bug 1846641 Change-Id: I738489627e76855328bb2d5ffb2fac1ec8c53dc8 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1473698 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Tested-by: Terje Bergstrom Reviewed-by: Konsta Holtta Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index de14f1dd..c3d4ac3f 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -27,6 +27,8 @@ #include "gm20b/gr_gm20b.h" +#include "gp10b/priv_ring_gp10b.h" + #include "hal_gv11b.h" #include "bus_gv11b.h" #include "gr_gv11b.h" @@ -191,6 +193,7 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_bus(gops); gv11b_init_mc(gops); + gp10b_init_priv_ring(gops); gv11b_init_ltc(gops); gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); -- cgit v1.2.2 From 8da78a9fa7826985e8ca08a0a15eb1d6f38a222e Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 31 May 2017 13:29:06 +0530 Subject: gpu: nvgpu: include Include explicitly wherever the debug operations are used Jira NVGPU-62 Change-Id: I1845e08774b7c211e7fd954937708905f905e069 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1492818 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index c3d4ac3f..0cdb471b 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -46,6 +46,8 @@ #include "gv11b_gating_reglist.h" #include "regops_gv11b.h" +#include + #include static struct gpu_ops gv11b_ops; -- cgit v1.2.2 From a64984e7592bcd60a2dad1be8f1d24700a2e54de Mon Sep 17 00:00:00 2001 From: Sunny He Date: Thu, 22 Jun 2017 16:46:48 -0700 Subject: gpu: nvgpu: Reorganize ltc HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the ltc sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: If8760efb7d8e94b63dc6f1fe9efec4ddf49c0b29 Signed-off-by: Sunny He Reviewed-on: https://git-master/r/1507563 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 0cdb471b..35b1fdc5 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -25,8 +25,10 @@ #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" +#include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" +#include "gp10b/ltc_gp10b.h" #include "gp10b/priv_ring_gp10b.h" #include "hal_gv11b.h" @@ -50,9 +52,23 @@ #include -static struct gpu_ops gv11b_ops; - -static struct gpu_ops gv11b_ops = { +static const struct gpu_ops gv11b_ops = { + .ltc = { + .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, + .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, + .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, + .init_cbc = NULL, + .init_fs_state = gv11b_ltc_init_fs_state, + .init_comptags = gp10b_ltc_init_comptags, + .cbc_ctrl = gm20b_ltc_cbc_ctrl, + .isr = gv11b_ltc_isr, + .cbc_fix_config = gv11b_ltc_cbc_fix_config, + .flush = gm20b_flush_ltc, +#ifdef CONFIG_DEBUG_FS + .sync_debugfs = gp10b_ltc_sync_debugfs, +#endif + }, .clock_gating = { .slcg_bus_load_gating_prod = gv11b_slcg_bus_load_gating_prod, @@ -187,6 +203,7 @@ int gv11b_init_hal(struct gk20a *g) struct gpu_ops *gops = &g->ops; struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + gops->ltc = gv11b_ops.ltc; gops->clock_gating = gv11b_ops.clock_gating; /* boot in non-secure modes for time beeing */ @@ -196,7 +213,6 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_bus(gops); gv11b_init_mc(gops); gp10b_init_priv_ring(gops); - gv11b_init_ltc(gops); gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); gv11b_init_fb(gops); -- cgit v1.2.2 From 56eaeab512fb848492d398e62ef55a2c963cc7a6 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 3 May 2017 16:08:14 -0700 Subject: gpu: nvgpu: gv11b: sm stride litter added Required to support multiple SM JIRA GPUT19X-75 Change-Id: I1fd0530550ae14270a5e746d2efbf3e913ac4c3e Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1475985 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: David Martinez Nieto --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 35b1fdc5..0e874c8a 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -191,6 +191,10 @@ static int gv11b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_FBPA_STRIDE: ret = proj_fbpa_stride_v(); break; + case GPU_LIT_SM_PRI_STRIDE: + ret = proj_sm_stride_v(); + break; + default: break; } -- cgit v1.2.2 From c9b92595b2ac50dbfc2f6e2f9998d469b5ab4fbe Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 28 Jun 2017 16:00:52 -0700 Subject: gpu: nvgpu: gv11b: Reorg misc HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch covers the lone function pointers of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I098559103ef280faca4e82708bb47b9b37057cfd Signed-off-by: Sunny He Reviewed-on: https://git-master/r/1510390 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 147 +++++++++++++++++++----------------- 1 file changed, 76 insertions(+), 71 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 0e874c8a..98350e4b 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -52,75 +52,6 @@ #include -static const struct gpu_ops gv11b_ops = { - .ltc = { - .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, - .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, - .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, - .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, - .init_cbc = NULL, - .init_fs_state = gv11b_ltc_init_fs_state, - .init_comptags = gp10b_ltc_init_comptags, - .cbc_ctrl = gm20b_ltc_cbc_ctrl, - .isr = gv11b_ltc_isr, - .cbc_fix_config = gv11b_ltc_cbc_fix_config, - .flush = gm20b_flush_ltc, -#ifdef CONFIG_DEBUG_FS - .sync_debugfs = gp10b_ltc_sync_debugfs, -#endif - }, - .clock_gating = { - .slcg_bus_load_gating_prod = - gv11b_slcg_bus_load_gating_prod, - .slcg_ce2_load_gating_prod = - gv11b_slcg_ce2_load_gating_prod, - .slcg_chiplet_load_gating_prod = - gv11b_slcg_chiplet_load_gating_prod, - .slcg_ctxsw_firmware_load_gating_prod = - gv11b_slcg_ctxsw_firmware_load_gating_prod, - .slcg_fb_load_gating_prod = - gv11b_slcg_fb_load_gating_prod, - .slcg_fifo_load_gating_prod = - gv11b_slcg_fifo_load_gating_prod, - .slcg_gr_load_gating_prod = - gr_gv11b_slcg_gr_load_gating_prod, - .slcg_ltc_load_gating_prod = - ltc_gv11b_slcg_ltc_load_gating_prod, - .slcg_perf_load_gating_prod = - gv11b_slcg_perf_load_gating_prod, - .slcg_priring_load_gating_prod = - gv11b_slcg_priring_load_gating_prod, - .slcg_pmu_load_gating_prod = - gv11b_slcg_pmu_load_gating_prod, - .slcg_therm_load_gating_prod = - gv11b_slcg_therm_load_gating_prod, - .slcg_xbar_load_gating_prod = - gv11b_slcg_xbar_load_gating_prod, - .blcg_bus_load_gating_prod = - gv11b_blcg_bus_load_gating_prod, - .blcg_ce_load_gating_prod = - gv11b_blcg_ce_load_gating_prod, - .blcg_ctxsw_firmware_load_gating_prod = - gv11b_blcg_ctxsw_firmware_load_gating_prod, - .blcg_fb_load_gating_prod = - gv11b_blcg_fb_load_gating_prod, - .blcg_fifo_load_gating_prod = - gv11b_blcg_fifo_load_gating_prod, - .blcg_gr_load_gating_prod = - gv11b_blcg_gr_load_gating_prod, - .blcg_ltc_load_gating_prod = - gv11b_blcg_ltc_load_gating_prod, - .blcg_pwr_csb_load_gating_prod = - gv11b_blcg_pwr_csb_load_gating_prod, - .blcg_pmu_load_gating_prod = - gv11b_blcg_pmu_load_gating_prod, - .blcg_xbar_load_gating_prod = - gv11b_blcg_xbar_load_gating_prod, - .pg_gr_load_gating_prod = - gr_gv11b_pg_gr_load_gating_prod, - } -}; - static int gv11b_get_litter_value(struct gk20a *g, int value) { int ret = EINVAL; @@ -202,6 +133,77 @@ static int gv11b_get_litter_value(struct gk20a *g, int value) return ret; } +static const struct gpu_ops gv11b_ops = { + .ltc = { + .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, + .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, + .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, + .init_cbc = NULL, + .init_fs_state = gv11b_ltc_init_fs_state, + .init_comptags = gp10b_ltc_init_comptags, + .cbc_ctrl = gm20b_ltc_cbc_ctrl, + .isr = gv11b_ltc_isr, + .cbc_fix_config = gv11b_ltc_cbc_fix_config, + .flush = gm20b_flush_ltc, +#ifdef CONFIG_DEBUG_FS + .sync_debugfs = gp10b_ltc_sync_debugfs, +#endif + }, + .clock_gating = { + .slcg_bus_load_gating_prod = + gv11b_slcg_bus_load_gating_prod, + .slcg_ce2_load_gating_prod = + gv11b_slcg_ce2_load_gating_prod, + .slcg_chiplet_load_gating_prod = + gv11b_slcg_chiplet_load_gating_prod, + .slcg_ctxsw_firmware_load_gating_prod = + gv11b_slcg_ctxsw_firmware_load_gating_prod, + .slcg_fb_load_gating_prod = + gv11b_slcg_fb_load_gating_prod, + .slcg_fifo_load_gating_prod = + gv11b_slcg_fifo_load_gating_prod, + .slcg_gr_load_gating_prod = + gr_gv11b_slcg_gr_load_gating_prod, + .slcg_ltc_load_gating_prod = + ltc_gv11b_slcg_ltc_load_gating_prod, + .slcg_perf_load_gating_prod = + gv11b_slcg_perf_load_gating_prod, + .slcg_priring_load_gating_prod = + gv11b_slcg_priring_load_gating_prod, + .slcg_pmu_load_gating_prod = + gv11b_slcg_pmu_load_gating_prod, + .slcg_therm_load_gating_prod = + gv11b_slcg_therm_load_gating_prod, + .slcg_xbar_load_gating_prod = + gv11b_slcg_xbar_load_gating_prod, + .blcg_bus_load_gating_prod = + gv11b_blcg_bus_load_gating_prod, + .blcg_ce_load_gating_prod = + gv11b_blcg_ce_load_gating_prod, + .blcg_ctxsw_firmware_load_gating_prod = + gv11b_blcg_ctxsw_firmware_load_gating_prod, + .blcg_fb_load_gating_prod = + gv11b_blcg_fb_load_gating_prod, + .blcg_fifo_load_gating_prod = + gv11b_blcg_fifo_load_gating_prod, + .blcg_gr_load_gating_prod = + gv11b_blcg_gr_load_gating_prod, + .blcg_ltc_load_gating_prod = + gv11b_blcg_ltc_load_gating_prod, + .blcg_pwr_csb_load_gating_prod = + gv11b_blcg_pwr_csb_load_gating_prod, + .blcg_pmu_load_gating_prod = + gv11b_blcg_pmu_load_gating_prod, + .blcg_xbar_load_gating_prod = + gv11b_blcg_xbar_load_gating_prod, + .pg_gr_load_gating_prod = + gr_gv11b_pg_gr_load_gating_prod, + }, + .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, + .get_litter_value = gv11b_get_litter_value, +}; + int gv11b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; @@ -210,6 +212,11 @@ int gv11b_init_hal(struct gk20a *g) gops->ltc = gv11b_ops.ltc; gops->clock_gating = gv11b_ops.clock_gating; + /* Lone functions */ + gops->chip_init_gpu_characteristics = + gv11b_ops.chip_init_gpu_characteristics; + gops->get_litter_value = gv11b_ops.get_litter_value; + /* boot in non-secure modes for time beeing */ gops->privsecurity = 0; gops->securegpccs = 0; @@ -235,8 +242,6 @@ int gv11b_init_hal(struct gk20a *g) gk20a_init_css_ops(gops); #endif g->name = "gv11b"; - gops->chip_init_gpu_characteristics = gv11b_init_gpu_characteristics; - gops->get_litter_value = gv11b_get_litter_value; c->twod_class = FERMI_TWOD_A; c->threed_class = VOLTA_A; -- cgit v1.2.2 From aade61eff9962b4671802b0d88523e6ccccde6b0 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 28 Jun 2017 17:57:39 -0700 Subject: gpu: nvgpu: gv11b: Reorg falcon HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the falcon sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: If980fcd2605a445bd623a5fcca8262826ce289c4 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1514013 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 98350e4b..0a508ddf 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -200,6 +200,10 @@ static const struct gpu_ops gv11b_ops = { .pg_gr_load_gating_prod = gr_gv11b_pg_gr_load_gating_prod, }, + + .falcon = { + .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, + }, .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, .get_litter_value = gv11b_get_litter_value, }; @@ -211,6 +215,7 @@ int gv11b_init_hal(struct gk20a *g) gops->ltc = gv11b_ops.ltc; gops->clock_gating = gv11b_ops.clock_gating; + gops->falcon = gv11b_ops.falcon; /* Lone functions */ gops->chip_init_gpu_characteristics = @@ -231,7 +236,6 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_ce(gops); gv11b_init_gr_ctx(gops); gv11b_init_mm(gops); - gk20a_falcon_init_hal(gops); gv11b_init_pmu_ops(gops); gk20a_init_debug_ops(gops); gk20a_init_dbg_session_ops(gops); -- cgit v1.2.2 From 4e290320fdfe56cc2fe849720d6a01b44cace1a7 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Tue, 27 Jun 2017 14:05:15 -0700 Subject: gpu: nvgpu: gv11b: Reorg mc HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mc sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I1a5abde46bf079c206dfdf9f8ee35df048565c49 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1509603 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 0a508ddf..d7f00d2f 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -21,6 +21,7 @@ #include "gk20a/gk20a.h" #include "gk20a/css_gr_gk20a.h" +#include "gk20a/mc_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" @@ -29,6 +30,7 @@ #include "gm20b/gr_gm20b.h" #include "gp10b/ltc_gp10b.h" +#include "gp10b/mc_gp10b.h" #include "gp10b/priv_ring_gp10b.h" #include "hal_gv11b.h" @@ -200,7 +202,23 @@ static const struct gpu_ops gv11b_ops = { .pg_gr_load_gating_prod = gr_gv11b_pg_gr_load_gating_prod, }, - + .mc = { + .intr_enable = mc_gv11b_intr_enable, + .intr_unit_config = mc_gp10b_intr_unit_config, + .isr_stall = mc_gp10b_isr_stall, + .intr_stall = mc_gp10b_intr_stall, + .intr_stall_pause = mc_gp10b_intr_stall_pause, + .intr_stall_resume = mc_gp10b_intr_stall_resume, + .intr_nonstall = mc_gp10b_intr_nonstall, + .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, + .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, + .enable = gk20a_mc_enable, + .disable = gk20a_mc_disable, + .reset = gk20a_mc_reset, + .boot_0 = gk20a_mc_boot_0, + .is_intr1_pending = mc_gp10b_is_intr1_pending, + .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, + }, .falcon = { .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, }, @@ -215,6 +233,7 @@ int gv11b_init_hal(struct gk20a *g) gops->ltc = gv11b_ops.ltc; gops->clock_gating = gv11b_ops.clock_gating; + gops->mc = gv11b_ops.mc; gops->falcon = gv11b_ops.falcon; /* Lone functions */ @@ -227,7 +246,6 @@ int gv11b_init_hal(struct gk20a *g) gops->securegpccs = 0; gv11b_init_bus(gops); - gv11b_init_mc(gops); gp10b_init_priv_ring(gops); gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); -- cgit v1.2.2 From 4074484f756734d9f1902944dc80966f3659bb39 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Thu, 29 Jun 2017 11:14:52 -0700 Subject: gpu: nvgpu: gv11b: Reorg debug HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch covers the debug and dbg_session_ops sub-modules of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I23cda2fbb47fb41975a4a938e352a7427853be94 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1514820 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index d7f00d2f..18cd686e 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -25,6 +25,7 @@ #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" +#include "gk20a/regops_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" @@ -219,6 +220,21 @@ static const struct gpu_ops gv11b_ops = { .is_intr1_pending = mc_gp10b_is_intr1_pending, .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, }, + .debug = { + .show_dump = gk20a_debug_show_dump, + }, + .dbg_session_ops = { + .exec_reg_ops = exec_regops_gk20a, + .dbg_set_powergate = dbg_set_powergate, + .check_and_set_global_reservation = + nvgpu_check_and_set_global_reservation, + .check_and_set_context_reservation = + nvgpu_check_and_set_context_reservation, + .release_profiler_reservation = + nvgpu_release_profiler_reservation, + .perfbuffer_enable = gk20a_perfbuf_enable_locked, + .perfbuffer_disable = gk20a_perfbuf_disable_locked, + }, .falcon = { .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, }, @@ -234,6 +250,8 @@ int gv11b_init_hal(struct gk20a *g) gops->ltc = gv11b_ops.ltc; gops->clock_gating = gv11b_ops.clock_gating; gops->mc = gv11b_ops.mc; + gops->debug = gv11b_ops.debug; + gops->dbg_session_ops = gv11b_ops.dbg_session_ops; gops->falcon = gv11b_ops.falcon; /* Lone functions */ @@ -255,8 +273,6 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_gr_ctx(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(gops); - gk20a_init_debug_ops(gops); - gk20a_init_dbg_session_ops(gops); gv11b_init_regops(gops); gv11b_init_therm_ops(gops); gk20a_init_tsg_ops(gops); -- cgit v1.2.2 From 3b7d50ee12b7ed93f908338dc321bf71023d4b49 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 5 Jul 2017 15:20:14 -0700 Subject: gpu: nvgpu: gv11b: Reorg css HAL init Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the css sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Change-Id: I04177d6c9eb4f3c433d493c815ad15cf7b755910 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1514206 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 18cd686e..4f993494 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -235,6 +235,16 @@ static const struct gpu_ops gv11b_ops = { .perfbuffer_enable = gk20a_perfbuf_enable_locked, .perfbuffer_disable = gk20a_perfbuf_disable_locked, }, +#if defined(CONFIG_GK20A_CYCLE_STATS) + .css = { + .enable_snapshot = css_hw_enable_snapshot, + .disable_snapshot = css_hw_disable_snapshot, + .check_data_available = css_hw_check_data_available, + .set_handled_snapshots = css_hw_set_handled_snapshots, + .allocate_perfmon_ids = css_gr_allocate_perfmon_ids, + .release_perfmon_ids = css_gr_release_perfmon_ids, + }, +#endif .falcon = { .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, }, @@ -252,6 +262,9 @@ int gv11b_init_hal(struct gk20a *g) gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; gops->dbg_session_ops = gv11b_ops.dbg_session_ops; +#if defined(CONFIG_GK20A_CYCLE_STATS) + gops->css = gv11b_ops.css; +#endif gops->falcon = gv11b_ops.falcon; /* Lone functions */ @@ -276,9 +289,7 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_regops(gops); gv11b_init_therm_ops(gops); gk20a_init_tsg_ops(gops); -#if defined(CONFIG_GK20A_CYCLE_STATS) - gk20a_init_css_ops(gops); -#endif + g->name = "gv11b"; c->twod_class = FERMI_TWOD_A; -- cgit v1.2.2 From e932982853d779b62bc328eb3e9e506dad590f64 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 5 Jul 2017 19:05:45 -0700 Subject: gpu: nvgpu: gv11b: Reorg bus HAL init Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the bus sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I469113b204cb693a6b1cbf34a9ca53b62e34ec20 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1514661 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 4f993494..51fe6b0a 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -35,7 +35,6 @@ #include "gp10b/priv_ring_gp10b.h" #include "hal_gv11b.h" -#include "bus_gv11b.h" #include "gr_gv11b.h" #include "mc_gv11b.h" #include "ltc_gv11b.h" @@ -235,6 +234,12 @@ static const struct gpu_ops gv11b_ops = { .perfbuffer_enable = gk20a_perfbuf_enable_locked, .perfbuffer_disable = gk20a_perfbuf_disable_locked, }, + .bus = { + .init_hw = gk20a_bus_init_hw, + .isr = gk20a_bus_isr, + .read_ptimer = gk20a_read_ptimer, + .bar1_bind = NULL, + }, #if defined(CONFIG_GK20A_CYCLE_STATS) .css = { .enable_snapshot = css_hw_enable_snapshot, @@ -262,6 +267,7 @@ int gv11b_init_hal(struct gk20a *g) gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; gops->dbg_session_ops = gv11b_ops.dbg_session_ops; + gops->bus = gv11b_ops.bus; #if defined(CONFIG_GK20A_CYCLE_STATS) gops->css = gv11b_ops.css; #endif @@ -276,7 +282,6 @@ int gv11b_init_hal(struct gk20a *g) gops->privsecurity = 0; gops->securegpccs = 0; - gv11b_init_bus(gops); gp10b_init_priv_ring(gops); gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); -- cgit v1.2.2 From d9f906c1e0f06f54e545727817d227a0bac46a0a Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 28 Jun 2017 17:42:59 -0700 Subject: gpu: nvgpu: gv11b: Reorg priv_ring HAL init Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the priv_ring sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Idee9e8a3a5bfa65b350f0e9fb14c4364c4d6f1d2 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1514103 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 51fe6b0a..8dc9900a 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -253,6 +253,9 @@ static const struct gpu_ops gv11b_ops = { .falcon = { .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, }, + .priv_ring = { + .isr = gp10b_priv_ring_isr, + }, .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, .get_litter_value = gv11b_get_litter_value, }; @@ -272,6 +275,7 @@ int gv11b_init_hal(struct gk20a *g) gops->css = gv11b_ops.css; #endif gops->falcon = gv11b_ops.falcon; + gops->priv_ring = gv11b_ops.priv_ring; /* Lone functions */ gops->chip_init_gpu_characteristics = @@ -282,7 +286,6 @@ int gv11b_init_hal(struct gk20a *g) gops->privsecurity = 0; gops->securegpccs = 0; - gp10b_init_priv_ring(gops); gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); gv11b_init_fb(gops); -- cgit v1.2.2 From 8140c51e6cd212517fc343e6f8f8694bbad98f3b Mon Sep 17 00:00:00 2001 From: Sunny He Date: Fri, 30 Jun 2017 15:54:03 -0700 Subject: gpu: nvgpu: gv11b: Reorg fifo HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fifo sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I7c81edfa785a4ecafef41aae7b82d6b1707d294e Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1522554 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 76 ++++++++++++++++++++++++++++++++++++- 1 file changed, 74 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 8dc9900a..b6c17c7d 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -20,6 +20,7 @@ #include #include "gk20a/gk20a.h" +#include "gk20a/fifo_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/mc_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" @@ -29,10 +30,12 @@ #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" +#include "gm20b/fifo_gm20b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/mc_gp10b.h" #include "gp10b/priv_ring_gp10b.h" +#include "gp10b/fifo_gp10b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -49,10 +52,14 @@ #include "fifo_gv11b.h" #include "gv11b_gating_reglist.h" #include "regops_gv11b.h" +#include "subctx_gv11b.h" #include #include +#include +#include +#include static int gv11b_get_litter_value(struct gk20a *g, int value) { @@ -202,6 +209,72 @@ static const struct gpu_ops gv11b_ops = { .pg_gr_load_gating_prod = gr_gv11b_pg_gr_load_gating_prod, }, + .fifo = { + .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, + .bind_channel = channel_gm20b_bind, + .unbind_channel = channel_gv11b_unbind, + .disable_channel = gk20a_fifo_disable_channel, + .enable_channel = gk20a_fifo_enable_channel, + .alloc_inst = gk20a_fifo_alloc_inst, + .free_inst = gk20a_fifo_free_inst, + .setup_ramfc = channel_gv11b_setup_ramfc, + .channel_set_priority = gk20a_fifo_set_priority, + .channel_set_timeslice = gk20a_fifo_set_timeslice, + .default_timeslice_us = gk20a_fifo_default_timeslice_us, + .setup_userd = gk20a_fifo_setup_userd, + .userd_gp_get = gv11b_userd_gp_get, + .userd_gp_put = gv11b_userd_gp_put, + .userd_pb_get = gv11b_userd_pb_get, + .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, + .preempt_channel = gv11b_fifo_preempt_channel, + .preempt_tsg = gv11b_fifo_preempt_tsg, + .update_runlist = gk20a_fifo_update_runlist, + .trigger_mmu_fault = NULL, + .get_mmu_fault_info = NULL, + .wait_engine_idle = gk20a_fifo_wait_engine_idle, + .get_num_fifos = gv11b_fifo_get_num_fifos, + .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, + .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, + .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, + .force_reset_ch = gk20a_fifo_force_reset_ch, + .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, + .device_info_data_parse = gp10b_device_info_data_parse, + .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, + .init_engine_info = gk20a_fifo_init_engine_info, + .runlist_entry_size = ram_rl_entry_size_v, + .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry, + .get_ch_runlist_entry = gv11b_get_ch_runlist_entry, + .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, + .dump_pbdma_status = gk20a_dump_pbdma_status, + .dump_eng_status = gv11b_dump_eng_status, + .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc, + .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, + .is_preempt_pending = gv11b_fifo_is_preempt_pending, + .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, + .reset_enable_hw = gv11b_init_fifo_reset_enable_hw, + .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, + .handle_sched_error = gv11b_fifo_handle_sched_error, + .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, + .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, + .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers, + .deinit_eng_method_buffers = + gv11b_fifo_deinit_eng_method_buffers, + .tsg_bind_channel = gk20a_tsg_bind_channel, + .tsg_unbind_channel = gk20a_tsg_unbind_channel, +#ifdef CONFIG_TEGRA_GK20A_NVHOST + .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, + .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, + .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd, + .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, + .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, + .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, +#endif + .resetup_ramfc = NULL, + .device_info_fault_id = top_device_info_data_fault_id_enum_v, + .free_channel_ctx_header = gv11b_free_subctx_header, + .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg, + .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, + }, .mc = { .intr_enable = mc_gv11b_intr_enable, .intr_unit_config = mc_gp10b_intr_unit_config, @@ -267,6 +340,7 @@ int gv11b_init_hal(struct gk20a *g) gops->ltc = gv11b_ops.ltc; gops->clock_gating = gv11b_ops.clock_gating; + gops->fifo = gv11b_ops.fifo; gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; gops->dbg_session_ops = gv11b_ops.dbg_session_ops; @@ -289,14 +363,12 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); gv11b_init_fb(gops); - gv11b_init_fifo(gops); gv11b_init_ce(gops); gv11b_init_gr_ctx(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(gops); gv11b_init_regops(gops); gv11b_init_therm_ops(gops); - gk20a_init_tsg_ops(gops); g->name = "gv11b"; -- cgit v1.2.2 From a5d6970df79ab712a7db76e7a02bceaa590ae1d9 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 28 Jun 2017 14:17:59 -0700 Subject: gpu: nvgpu: gv11b: Remove securegpccs from gpu_ops Replace securegpccs boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_SECUREGPCCS Jira NVGPU-74 Change-Id: I487aa5e8545027a3b5bbe33ce68b2715cc2eb39a Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1514096 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index b6c17c7d..2c20bd04 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -55,6 +55,7 @@ #include "subctx_gv11b.h" #include +#include #include #include @@ -358,7 +359,7 @@ int gv11b_init_hal(struct gk20a *g) /* boot in non-secure modes for time beeing */ gops->privsecurity = 0; - gops->securegpccs = 0; + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(gops); gv11b_init_fecs_trace_ops(gops); -- cgit v1.2.2 From 2b98e1308d49b9c941d8fa6fc87f67108d6d9370 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Mon, 24 Jul 2017 12:19:53 -0700 Subject: gpu: nvgpu: gv11b: Remove privsecurity from gpu_ops Replace privsecurity boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_PRIVSECURITY Jira NVGPU-74 Change-Id: I4c11e3a89a76abe137cf61b69ad0fbcd665554b7 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1525714 Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 2c20bd04..3ebeb205 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -358,16 +358,16 @@ int gv11b_init_hal(struct gk20a *g) gops->get_litter_value = gv11b_ops.get_litter_value; /* boot in non-secure modes for time beeing */ - gops->privsecurity = 0; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); - gv11b_init_gr(gops); + gv11b_init_gr(g); gv11b_init_fecs_trace_ops(gops); gv11b_init_fb(gops); gv11b_init_ce(gops); gv11b_init_gr_ctx(gops); gv11b_init_mm(gops); - gv11b_init_pmu_ops(gops); + gv11b_init_pmu_ops(g); gv11b_init_regops(gops); gv11b_init_therm_ops(gops); -- cgit v1.2.2 From 3c556c5e9573ffa69bfe64ed1401ed4a9141acb3 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Tue, 27 Jun 2017 15:09:58 -0700 Subject: gpu: nvgpu: gv11b: Reorg ce2 HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the ce2 sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ia2d715a471d7e23420691a461e9442780176ea13 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1509633 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 3ebeb205..e585e9b1 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -34,6 +34,7 @@ #include "gp10b/ltc_gp10b.h" #include "gp10b/mc_gp10b.h" +#include "gp10b/ce_gp10b.h" #include "gp10b/priv_ring_gp10b.h" #include "gp10b/fifo_gp10b.h" @@ -160,6 +161,11 @@ static const struct gpu_ops gv11b_ops = { .sync_debugfs = gp10b_ltc_sync_debugfs, #endif }, + .ce2 = { + .isr_stall = gv11b_ce_isr, + .isr_nonstall = gp10b_ce_nonstall_isr, + .get_num_pce = gv11b_ce_get_num_pce, + }, .clock_gating = { .slcg_bus_load_gating_prod = gv11b_slcg_bus_load_gating_prod, @@ -340,6 +346,7 @@ int gv11b_init_hal(struct gk20a *g) struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; gops->ltc = gv11b_ops.ltc; + gops->ce2 = gv11b_ops.ce2; gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; gops->mc = gv11b_ops.mc; @@ -364,7 +371,6 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_gr(g); gv11b_init_fecs_trace_ops(gops); gv11b_init_fb(gops); - gv11b_init_ce(gops); gv11b_init_gr_ctx(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(g); -- cgit v1.2.2 From afa29933e45b2c3054db67065a0a68606bbc1f52 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 26 Jul 2017 10:45:38 -0700 Subject: gpu: nvgpu: gv11b: Reorg gr_ctx HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the gr_ctx sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Icc6b0f968f2e3209de190d445c878a4b20bfcf4a Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1527418 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index e585e9b1..f5191da7 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -282,6 +282,10 @@ static const struct gpu_ops gv11b_ops = { .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg, .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, }, + .gr_ctx = { + .get_netlist_name = gr_gv11b_get_netlist_name, + .is_fw_defined = gr_gv11b_is_firmware_defined, + }, .mc = { .intr_enable = mc_gv11b_intr_enable, .intr_unit_config = mc_gp10b_intr_unit_config, @@ -349,6 +353,7 @@ int gv11b_init_hal(struct gk20a *g) gops->ce2 = gv11b_ops.ce2; gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; + gops->gr_ctx = gv11b_ops.gr_ctx; gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; gops->dbg_session_ops = gv11b_ops.dbg_session_ops; @@ -365,13 +370,13 @@ int gv11b_init_hal(struct gk20a *g) gops->get_litter_value = gv11b_ops.get_litter_value; /* boot in non-secure modes for time beeing */ + __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false); __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(g); gv11b_init_fecs_trace_ops(gops); gv11b_init_fb(gops); - gv11b_init_gr_ctx(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(g); gv11b_init_regops(gops); -- cgit v1.2.2 From 8aa0370005a81a7e26ae7c86585626d3261aa4d3 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 26 Jul 2017 11:14:21 -0700 Subject: gpu: nvgpu: gv11b: Reorg fecs_trace HAL init Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fecs_trace sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I43932a8eac2a9f791e967a8ed736f76350889a51 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1527420 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index f5191da7..04712409 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -21,6 +21,8 @@ #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" +#include "gk20a/ctxsw_trace_gk20a.h" +#include "gk20a/fecs_trace_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/mc_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" @@ -37,12 +39,12 @@ #include "gp10b/ce_gp10b.h" #include "gp10b/priv_ring_gp10b.h" #include "gp10b/fifo_gp10b.h" +#include "gp10b/fecs_trace_gp10b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" #include "mc_gv11b.h" #include "ltc_gv11b.h" -#include "fecs_trace_gv11b.h" #include "gv11b.h" #include "ce_gv11b.h" #include "gr_ctx_gv11b.h" @@ -286,6 +288,24 @@ static const struct gpu_ops gv11b_ops = { .get_netlist_name = gr_gv11b_get_netlist_name, .is_fw_defined = gr_gv11b_is_firmware_defined, }, +#ifdef CONFIG_GK20A_CTXSW_TRACE + .fecs_trace = { + .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc, + .free_user_buffer = gk20a_ctxsw_dev_ring_free, + .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer, + .init = gk20a_fecs_trace_init, + .deinit = gk20a_fecs_trace_deinit, + .enable = gk20a_fecs_trace_enable, + .disable = gk20a_fecs_trace_disable, + .is_enabled = gk20a_fecs_trace_is_enabled, + .reset = gk20a_fecs_trace_reset, + .flush = gp10b_fecs_trace_flush, + .poll = gk20a_fecs_trace_poll, + .bind_channel = gk20a_fecs_trace_bind_channel, + .unbind_channel = gk20a_fecs_trace_unbind_channel, + .max_entries = gk20a_gr_max_entries, + }, +#endif /* CONFIG_GK20A_CTXSW_TRACE */ .mc = { .intr_enable = mc_gv11b_intr_enable, .intr_unit_config = mc_gp10b_intr_unit_config, @@ -354,6 +374,7 @@ int gv11b_init_hal(struct gk20a *g) gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; + gops->fecs_trace = gv11b_ops.fecs_trace; gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; gops->dbg_session_ops = gv11b_ops.dbg_session_ops; @@ -375,7 +396,6 @@ int gv11b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(g); - gv11b_init_fecs_trace_ops(gops); gv11b_init_fb(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(g); -- cgit v1.2.2 From f457e808f0d1097cec02a022eb42c77a075ef881 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 26 Jul 2017 18:09:07 -0700 Subject: gpu: nvgpu: gv11b: Reorg therm HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the therm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ic297792c4d47ffbe64cc0bd95a659a6b7f383743 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1527423 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 04712409..f6121f94 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -35,6 +35,7 @@ #include "gm20b/fifo_gm20b.h" #include "gp10b/ltc_gp10b.h" +#include "gp10b/therm_gp10b.h" #include "gp10b/mc_gp10b.h" #include "gp10b/ce_gp10b.h" #include "gp10b/priv_ring_gp10b.h" @@ -50,7 +51,6 @@ #include "gr_ctx_gv11b.h" #include "mm_gv11b.h" #include "pmu_gv11b.h" -#include "therm_gv11b.h" #include "fb_gv11b.h" #include "fifo_gv11b.h" #include "gv11b_gating_reglist.h" @@ -306,6 +306,10 @@ static const struct gpu_ops gv11b_ops = { .max_entries = gk20a_gr_max_entries, }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ + .therm = { + .init_therm_setup_hw = gp10b_init_therm_setup_hw, + .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, + }, .mc = { .intr_enable = mc_gv11b_intr_enable, .intr_unit_config = mc_gp10b_intr_unit_config, @@ -375,6 +379,7 @@ int gv11b_init_hal(struct gk20a *g) gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; gops->fecs_trace = gv11b_ops.fecs_trace; + gops->therm = gv11b_ops.therm; gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; gops->dbg_session_ops = gv11b_ops.dbg_session_ops; @@ -400,7 +405,6 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_mm(gops); gv11b_init_pmu_ops(g); gv11b_init_regops(gops); - gv11b_init_therm_ops(gops); g->name = "gv11b"; -- cgit v1.2.2 From f87007829f176baa5d3e784c71f3bceb082a29eb Mon Sep 17 00:00:00 2001 From: Sunny He Date: Fri, 28 Jul 2017 18:37:49 -0700 Subject: gpu: nvgpu: gv11b: Reorg regops HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the regops sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ibf9f64ca445691e252b72c2b8fc59edb84e226ce Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1530136 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Tested-by: Alex Waterman Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index f6121f94..963f78c6 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -310,6 +310,29 @@ static const struct gpu_ops gv11b_ops = { .init_therm_setup_hw = gp10b_init_therm_setup_hw, .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, }, + .regops = { + .get_global_whitelist_ranges = + gv11b_get_global_whitelist_ranges, + .get_global_whitelist_ranges_count = + gv11b_get_global_whitelist_ranges_count, + .get_context_whitelist_ranges = + gv11b_get_context_whitelist_ranges, + .get_context_whitelist_ranges_count = + gv11b_get_context_whitelist_ranges_count, + .get_runcontrol_whitelist = gv11b_get_runcontrol_whitelist, + .get_runcontrol_whitelist_count = + gv11b_get_runcontrol_whitelist_count, + .get_runcontrol_whitelist_ranges = + gv11b_get_runcontrol_whitelist_ranges, + .get_runcontrol_whitelist_ranges_count = + gv11b_get_runcontrol_whitelist_ranges_count, + .get_qctl_whitelist = gv11b_get_qctl_whitelist, + .get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count, + .get_qctl_whitelist_ranges = gv11b_get_qctl_whitelist_ranges, + .get_qctl_whitelist_ranges_count = + gv11b_get_qctl_whitelist_ranges_count, + .apply_smpc_war = gv11b_apply_smpc_war, + }, .mc = { .intr_enable = mc_gv11b_intr_enable, .intr_unit_config = mc_gp10b_intr_unit_config, @@ -380,6 +403,7 @@ int gv11b_init_hal(struct gk20a *g) gops->gr_ctx = gv11b_ops.gr_ctx; gops->fecs_trace = gv11b_ops.fecs_trace; gops->therm = gv11b_ops.therm; + gops->regops = gv11b_ops.regops; gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; gops->dbg_session_ops = gv11b_ops.dbg_session_ops; @@ -404,7 +428,6 @@ int gv11b_init_hal(struct gk20a *g) gv11b_init_fb(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(g); - gv11b_init_regops(gops); g->name = "gv11b"; -- cgit v1.2.2 From 3e3c1920404ddec1ddbcf8adad93067f384a3e59 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 27 Jul 2017 13:00:46 -0700 Subject: gpu: nvgpu: gv11b: Make LTC disabling common code Refactor the sync_debugfs LTC HAL op so that the logic to enable or disable LTC goes to common code nvgpu_ltc_sync_enabled() and the LTC HAL set_enabled only performs the hardware register access. Create a new common function nvgpu_init_ltc_support() to initialize the LTC software variable, and move hardware initialization of LTC to be called from it. JIRA NVGPU-62 Change-Id: I7b73625bccd45aefa5694989adbf4a0bbac75fc4 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1529054 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 963f78c6..12ec4841 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -159,9 +159,7 @@ static const struct gpu_ops gv11b_ops = { .isr = gv11b_ltc_isr, .cbc_fix_config = gv11b_ltc_cbc_fix_config, .flush = gm20b_flush_ltc, -#ifdef CONFIG_DEBUG_FS - .sync_debugfs = gp10b_ltc_sync_debugfs, -#endif + .set_enabled = gp10b_ltc_set_enabled, }, .ce2 = { .isr_stall = gv11b_ce_isr, -- cgit v1.2.2 From 026d1f8efec6f88a6a910820b761ba1b335edc72 Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Fri, 4 Aug 2017 10:44:41 -0700 Subject: gpu: nvgpu: update gv11b_get_litter_value Update gv11b_get_litter_value: - add PPC_IN_GPC_BASE - set all FBPA values to 0, since gv11b does not have an FBPA unit - error/bug if we fall through to default, for easier debugging JIRA EVLR-1712 Change-Id: I9a388d6f525e101d4742ade07f972410ec3b2591 Signed-off-by: Peter Daifuku Reviewed-on: https://git-master.nvidia.com/r/1533192 Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 12ec4841..282aa228 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -105,6 +105,9 @@ static int gv11b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_TPC_IN_GPC_SHARED_BASE: ret = proj_tpc_in_gpc_shared_base_v(); break; + case GPU_LIT_PPC_IN_GPC_BASE: + ret = proj_ppc_in_gpc_base_v(); + break; case GPU_LIT_PPC_IN_GPC_STRIDE: ret = proj_ppc_in_gpc_stride_v(); break; @@ -129,17 +132,23 @@ static int gv11b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_LTS_STRIDE: ret = proj_lts_stride_v(); break; - case GPU_LIT_NUM_FBPAS: - ret = proj_scal_litter_num_fbpas_v(); - break; - case GPU_LIT_FBPA_STRIDE: - ret = proj_fbpa_stride_v(); - break; case GPU_LIT_SM_PRI_STRIDE: ret = proj_sm_stride_v(); break; + /* GV11B does not have a FBPA unit, despite what's listed in the + * hw headers or read back through NV_PTOP_SCAL_NUM_FBPAS, + * so hardcode all values to 0. + */ + case GPU_LIT_NUM_FBPAS: + case GPU_LIT_FBPA_STRIDE: + case GPU_LIT_FBPA_BASE: + case GPU_LIT_FBPA_SHARED_BASE: + ret = 0; + break; default: + nvgpu_err(g, "Missing definition %d", value); + BUG(); break; } -- cgit v1.2.2 From da8e67f042760d54f3d6b5f84abbd9981d9fcd54 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Mon, 31 Jul 2017 14:40:46 -0700 Subject: gpu: nvgpu: gv11b: Reorg fb HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fb sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I896d90e0dcffc0e133e6902ff9c3eab39c53080d Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1533354 Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 282aa228..9f6c67c1 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -29,9 +29,11 @@ #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" #include "gk20a/regops_gk20a.h" +#include "gk20a/fb_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" +#include "gm20b/fb_gm20b.h" #include "gm20b/fifo_gm20b.h" #include "gp10b/ltc_gp10b.h" @@ -41,6 +43,7 @@ #include "gp10b/priv_ring_gp10b.h" #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" +#include "gp10b/fb_gp10b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -175,6 +178,23 @@ static const struct gpu_ops gv11b_ops = { .isr_nonstall = gp10b_ce_nonstall_isr, .get_num_pce = gv11b_ce_get_num_pce, }, + .fb = { + .reset = gv11b_fb_reset, + .init_hw = gk20a_fb_init_hw, + .init_fs_state = gv11b_fb_init_fs_state, + .init_cbc = gv11b_fb_init_cbc, + .set_mmu_page_size = gm20b_fb_set_mmu_page_size, + .set_use_full_comp_tag_line = + gm20b_fb_set_use_full_comp_tag_line, + .compression_page_size = gp10b_fb_compression_page_size, + .compressible_page_size = gp10b_fb_compressible_page_size, + .vpr_info_fetch = gm20b_fb_vpr_info_fetch, + .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, + .set_debug_mode = gm20b_fb_set_debug_mode, + .tlb_invalidate = gk20a_fb_tlb_invalidate, + .hub_isr = gv11b_fb_hub_isr, + }, .clock_gating = { .slcg_bus_load_gating_prod = gv11b_slcg_bus_load_gating_prod, @@ -405,6 +425,7 @@ int gv11b_init_hal(struct gk20a *g) gops->ltc = gv11b_ops.ltc; gops->ce2 = gv11b_ops.ce2; + gops->fb = gv11b_ops.fb; gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; @@ -432,10 +453,12 @@ int gv11b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(g); - gv11b_init_fb(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(g); + gv11b_init_uncompressed_kind_map(); + gv11b_init_kind_attr(); + g->name = "gv11b"; c->twod_class = FERMI_TWOD_A; -- cgit v1.2.2 From 96615351ad11a186f5869e56acb3c1948ab7b7cc Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 26 Jul 2017 14:23:01 -0700 Subject: gpu: nvgpu: gv11b: Reorg mm HAL init Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ic2c7d56e552645f2125d9c60a817967be1e8e765 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1533355 Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 9f6c67c1..afc90aa7 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -25,6 +25,7 @@ #include "gk20a/fecs_trace_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/mc_gk20a.h" +#include "gk20a/mm_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" @@ -35,6 +36,7 @@ #include "gm20b/gr_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/fifo_gm20b.h" +#include "gm20b/mm_gm20b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/therm_gp10b.h" @@ -44,6 +46,7 @@ #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" #include "gp10b/fb_gp10b.h" +#include "gp10b/mm_gp10b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -60,6 +63,8 @@ #include "regops_gv11b.h" #include "subctx_gv11b.h" +#include "common/linux/platform_gk20a_tegra.h" + #include #include @@ -333,6 +338,31 @@ static const struct gpu_ops gv11b_ops = { .max_entries = gk20a_gr_max_entries, }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ + .mm = { + .support_sparse = gm20b_mm_support_sparse, + .gmmu_map = gk20a_locked_gmmu_map, + .gmmu_unmap = gk20a_locked_gmmu_unmap, + .vm_bind_channel = gk20a_vm_bind_channel, + .fb_flush = gk20a_mm_fb_flush, + .l2_invalidate = gk20a_mm_l2_invalidate, + .l2_flush = gv11b_mm_l2_flush, + .cbc_clean = gk20a_mm_cbc_clean, + .set_big_page_size = gm20b_mm_set_big_page_size, + .get_big_page_sizes = gm20b_mm_get_big_page_sizes, + .get_default_big_page_size = gp10b_mm_get_default_big_page_size, + .gpu_phys_addr = gv11b_gpu_phys_addr, + .get_physical_addr_bits = gp10b_mm_get_physical_addr_bits, + .get_mmu_levels = gp10b_mm_get_mmu_levels, + .init_pdb = gp10b_mm_init_pdb, + .init_mm_setup_hw = gv11b_init_mm_setup_hw, + .is_bar1_supported = gv11b_mm_is_bar1_supported, + .init_inst_block = gv11b_init_inst_block, + .mmu_fault_pending = gv11b_mm_mmu_fault_pending, + .init_bar2_vm = gb10b_init_bar2_vm, + .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, + .remove_bar2_vm = gv11b_mm_remove_bar2_vm, + .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, + }, .therm = { .init_therm_setup_hw = gp10b_init_therm_setup_hw, .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, @@ -429,6 +459,7 @@ int gv11b_init_hal(struct gk20a *g) gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; + gops->mm = gv11b_ops.mm; gops->fecs_trace = gv11b_ops.fecs_trace; gops->therm = gv11b_ops.therm; gops->regops = gv11b_ops.regops; @@ -453,7 +484,6 @@ int gv11b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(g); - gv11b_init_mm(gops); gv11b_init_pmu_ops(g); gv11b_init_uncompressed_kind_map(); -- cgit v1.2.2 From a4e095aa37ec5a6c09a8cc6477da9fa49a73cd77 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Fri, 11 Aug 2017 14:40:58 -0700 Subject: Revert "gpu: nvgpu: gv11b: Reorg mm HAL init" This reverts commit 96615351ad11a186f5869e56acb3c1948ab7b7cc, which conflicts with gv100 changes. Change-Id: I08797bb23dd9226f0228ce3235fce6feef8d82f3 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1537667 Reviewed-by: Shu Zhong Tested-by: Shu Zhong --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 32 +------------------------------- 1 file changed, 1 insertion(+), 31 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index afc90aa7..9f6c67c1 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -25,7 +25,6 @@ #include "gk20a/fecs_trace_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/mc_gk20a.h" -#include "gk20a/mm_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" @@ -36,7 +35,6 @@ #include "gm20b/gr_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/fifo_gm20b.h" -#include "gm20b/mm_gm20b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/therm_gp10b.h" @@ -46,7 +44,6 @@ #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" #include "gp10b/fb_gp10b.h" -#include "gp10b/mm_gp10b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -63,8 +60,6 @@ #include "regops_gv11b.h" #include "subctx_gv11b.h" -#include "common/linux/platform_gk20a_tegra.h" - #include #include @@ -338,31 +333,6 @@ static const struct gpu_ops gv11b_ops = { .max_entries = gk20a_gr_max_entries, }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ - .mm = { - .support_sparse = gm20b_mm_support_sparse, - .gmmu_map = gk20a_locked_gmmu_map, - .gmmu_unmap = gk20a_locked_gmmu_unmap, - .vm_bind_channel = gk20a_vm_bind_channel, - .fb_flush = gk20a_mm_fb_flush, - .l2_invalidate = gk20a_mm_l2_invalidate, - .l2_flush = gv11b_mm_l2_flush, - .cbc_clean = gk20a_mm_cbc_clean, - .set_big_page_size = gm20b_mm_set_big_page_size, - .get_big_page_sizes = gm20b_mm_get_big_page_sizes, - .get_default_big_page_size = gp10b_mm_get_default_big_page_size, - .gpu_phys_addr = gv11b_gpu_phys_addr, - .get_physical_addr_bits = gp10b_mm_get_physical_addr_bits, - .get_mmu_levels = gp10b_mm_get_mmu_levels, - .init_pdb = gp10b_mm_init_pdb, - .init_mm_setup_hw = gv11b_init_mm_setup_hw, - .is_bar1_supported = gv11b_mm_is_bar1_supported, - .init_inst_block = gv11b_init_inst_block, - .mmu_fault_pending = gv11b_mm_mmu_fault_pending, - .init_bar2_vm = gb10b_init_bar2_vm, - .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, - .remove_bar2_vm = gv11b_mm_remove_bar2_vm, - .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, - }, .therm = { .init_therm_setup_hw = gp10b_init_therm_setup_hw, .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, @@ -459,7 +429,6 @@ int gv11b_init_hal(struct gk20a *g) gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; - gops->mm = gv11b_ops.mm; gops->fecs_trace = gv11b_ops.fecs_trace; gops->therm = gv11b_ops.therm; gops->regops = gv11b_ops.regops; @@ -484,6 +453,7 @@ int gv11b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(g); + gv11b_init_mm(gops); gv11b_init_pmu_ops(g); gv11b_init_uncompressed_kind_map(); -- cgit v1.2.2 From 6486d4b8f1c9750f039374db00477e0af167cfbe Mon Sep 17 00:00:00 2001 From: Sunny He Date: Fri, 11 Aug 2017 14:41:50 -0700 Subject: Revert "gpu: nvgpu: gv11b: Reorg fb HAL initialization" Conflicts with gv100 changes This reverts commit da8e67f042760d54f3d6b5f84abbd9981d9fcd54. Change-Id: Ifd1a51debc0e92fc443e6ac0aad1b224821d6585 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1537669 Reviewed-by: Shu Zhong Tested-by: Shu Zhong --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 25 +------------------------ 1 file changed, 1 insertion(+), 24 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 9f6c67c1..282aa228 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -29,11 +29,9 @@ #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" #include "gk20a/regops_gk20a.h" -#include "gk20a/fb_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" -#include "gm20b/fb_gm20b.h" #include "gm20b/fifo_gm20b.h" #include "gp10b/ltc_gp10b.h" @@ -43,7 +41,6 @@ #include "gp10b/priv_ring_gp10b.h" #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" -#include "gp10b/fb_gp10b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -178,23 +175,6 @@ static const struct gpu_ops gv11b_ops = { .isr_nonstall = gp10b_ce_nonstall_isr, .get_num_pce = gv11b_ce_get_num_pce, }, - .fb = { - .reset = gv11b_fb_reset, - .init_hw = gk20a_fb_init_hw, - .init_fs_state = gv11b_fb_init_fs_state, - .init_cbc = gv11b_fb_init_cbc, - .set_mmu_page_size = gm20b_fb_set_mmu_page_size, - .set_use_full_comp_tag_line = - gm20b_fb_set_use_full_comp_tag_line, - .compression_page_size = gp10b_fb_compression_page_size, - .compressible_page_size = gp10b_fb_compressible_page_size, - .vpr_info_fetch = gm20b_fb_vpr_info_fetch, - .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, - .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, - .set_debug_mode = gm20b_fb_set_debug_mode, - .tlb_invalidate = gk20a_fb_tlb_invalidate, - .hub_isr = gv11b_fb_hub_isr, - }, .clock_gating = { .slcg_bus_load_gating_prod = gv11b_slcg_bus_load_gating_prod, @@ -425,7 +405,6 @@ int gv11b_init_hal(struct gk20a *g) gops->ltc = gv11b_ops.ltc; gops->ce2 = gv11b_ops.ce2; - gops->fb = gv11b_ops.fb; gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; @@ -453,12 +432,10 @@ int gv11b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(g); + gv11b_init_fb(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(g); - gv11b_init_uncompressed_kind_map(); - gv11b_init_kind_attr(); - g->name = "gv11b"; c->twod_class = FERMI_TWOD_A; -- cgit v1.2.2 From 78f1dac924221c9edbe51504b77e51caf2da7179 Mon Sep 17 00:00:00 2001 From: Sandarbh Jain Date: Wed, 9 Aug 2017 14:59:00 -0700 Subject: gpu: nvgpu: gv11b: PPC_IN_GPC_SHARED_BASE litter Adding missing GPU_LIT_PPC_IN_GPC_SHARED_BASE litter value Bug 1971835 Change-Id: If8851971ebea685fd6b3515b740aba8b64cae067 Signed-off-by: Sandarbh Jain Reviewed-on: https://git-master.nvidia.com/r/1536084 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 282aa228..7c38b611 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -108,6 +108,9 @@ static int gv11b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_PPC_IN_GPC_BASE: ret = proj_ppc_in_gpc_base_v(); break; + case GPU_LIT_PPC_IN_GPC_SHARED_BASE: + ret = proj_ppc_in_gpc_shared_base_v(); + break; case GPU_LIT_PPC_IN_GPC_STRIDE: ret = proj_ppc_in_gpc_stride_v(); break; -- cgit v1.2.2 From 4bb0896912440d126ae47da350b448f37dabc63d Mon Sep 17 00:00:00 2001 From: Sunny He Date: Mon, 31 Jul 2017 14:40:46 -0700 Subject: gpu: nvgpu: Reorg fb HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fb sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I3fdbf6059ef664caf8d33797a8a5f3f8eb6485bf Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1537748 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 7c38b611..14b7a541 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -29,9 +29,11 @@ #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" #include "gk20a/regops_gk20a.h" +#include "gk20a/fb_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" +#include "gm20b/fb_gm20b.h" #include "gm20b/fifo_gm20b.h" #include "gp10b/ltc_gp10b.h" @@ -41,6 +43,7 @@ #include "gp10b/priv_ring_gp10b.h" #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" +#include "gp10b/fb_gp10b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -178,6 +181,23 @@ static const struct gpu_ops gv11b_ops = { .isr_nonstall = gp10b_ce_nonstall_isr, .get_num_pce = gv11b_ce_get_num_pce, }, + .fb = { + .reset = gv11b_fb_reset, + .init_hw = gk20a_fb_init_hw, + .init_fs_state = gv11b_fb_init_fs_state, + .init_cbc = gv11b_fb_init_cbc, + .set_mmu_page_size = gm20b_fb_set_mmu_page_size, + .set_use_full_comp_tag_line = + gm20b_fb_set_use_full_comp_tag_line, + .compression_page_size = gp10b_fb_compression_page_size, + .compressible_page_size = gp10b_fb_compressible_page_size, + .vpr_info_fetch = gm20b_fb_vpr_info_fetch, + .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, + .set_debug_mode = gm20b_fb_set_debug_mode, + .tlb_invalidate = gk20a_fb_tlb_invalidate, + .hub_isr = gv11b_fb_hub_isr, + }, .clock_gating = { .slcg_bus_load_gating_prod = gv11b_slcg_bus_load_gating_prod, @@ -408,6 +428,7 @@ int gv11b_init_hal(struct gk20a *g) gops->ltc = gv11b_ops.ltc; gops->ce2 = gv11b_ops.ce2; + gops->fb = gv11b_ops.fb; gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; @@ -435,10 +456,12 @@ int gv11b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(g); - gv11b_init_fb(gops); gv11b_init_mm(gops); gv11b_init_pmu_ops(g); + gv11b_init_uncompressed_kind_map(); + gv11b_init_kind_attr(); + g->name = "gv11b"; c->twod_class = FERMI_TWOD_A; -- cgit v1.2.2 From 8ab6445df5b24c200ac4e346684119a85008e0e3 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Wed, 26 Jul 2017 14:23:01 -0700 Subject: gpu: nvgpu: Reorg mm HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I5fd295c6473d5b4a6178c0c6be8fcf8f4c33f2e3 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1537754 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 14b7a541..f572084d 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -25,6 +25,7 @@ #include "gk20a/fecs_trace_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/mc_gk20a.h" +#include "gk20a/mm_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" @@ -35,6 +36,7 @@ #include "gm20b/gr_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/fifo_gm20b.h" +#include "gm20b/mm_gm20b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/therm_gp10b.h" @@ -44,6 +46,7 @@ #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" #include "gp10b/fb_gp10b.h" +#include "gp10b/mm_gp10b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -336,6 +339,31 @@ static const struct gpu_ops gv11b_ops = { .max_entries = gk20a_gr_max_entries, }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ + .mm = { + .support_sparse = gm20b_mm_support_sparse, + .gmmu_map = gk20a_locked_gmmu_map, + .gmmu_unmap = gk20a_locked_gmmu_unmap, + .vm_bind_channel = gk20a_vm_bind_channel, + .fb_flush = gk20a_mm_fb_flush, + .l2_invalidate = gk20a_mm_l2_invalidate, + .l2_flush = gv11b_mm_l2_flush, + .cbc_clean = gk20a_mm_cbc_clean, + .set_big_page_size = gm20b_mm_set_big_page_size, + .get_big_page_sizes = gm20b_mm_get_big_page_sizes, + .get_default_big_page_size = gp10b_mm_get_default_big_page_size, + .gpu_phys_addr = gv11b_gpu_phys_addr, + .get_physical_addr_bits = gp10b_mm_get_physical_addr_bits, + .get_mmu_levels = gp10b_mm_get_mmu_levels, + .init_pdb = gp10b_mm_init_pdb, + .init_mm_setup_hw = gv11b_init_mm_setup_hw, + .is_bar1_supported = gv11b_mm_is_bar1_supported, + .init_inst_block = gv11b_init_inst_block, + .mmu_fault_pending = gv11b_mm_mmu_fault_pending, + .init_bar2_vm = gb10b_init_bar2_vm, + .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, + .remove_bar2_vm = gv11b_mm_remove_bar2_vm, + .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, + }, .therm = { .init_therm_setup_hw = gp10b_init_therm_setup_hw, .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, @@ -432,6 +460,7 @@ int gv11b_init_hal(struct gk20a *g) gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; + gops->mm = gv11b_ops.mm; gops->fecs_trace = gv11b_ops.fecs_trace; gops->therm = gv11b_ops.therm; gops->regops = gv11b_ops.regops; @@ -456,7 +485,6 @@ int gv11b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); gv11b_init_gr(g); - gv11b_init_mm(gops); gv11b_init_pmu_ops(g); gv11b_init_uncompressed_kind_map(); -- cgit v1.2.2 From cce0a55d2106865be14b3b39c083a0f55881f2a5 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Tue, 1 Aug 2017 17:12:03 -0700 Subject: gpu: nvgpu: gv11b: Reorg pmu HAL init Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the pmu sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I3f8a763a7bebf201c2242eecde7ff998aad07d0a Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1530983 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 67 +++++++++++++++++++++++++++++++++++-- 1 file changed, 65 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index f572084d..521cafa3 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -31,12 +31,15 @@ #include "gk20a/flcn_gk20a.h" #include "gk20a/regops_gk20a.h" #include "gk20a/fb_gk20a.h" +#include "gk20a/pmu_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/fifo_gm20b.h" #include "gm20b/mm_gm20b.h" +#include "gm20b/acr_gm20b.h" +#include "gm20b/pmu_gm20b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/therm_gp10b.h" @@ -47,6 +50,9 @@ #include "gp10b/fecs_trace_gp10b.h" #include "gp10b/fb_gp10b.h" #include "gp10b/mm_gp10b.h" +#include "gp10b/pmu_gp10b.h" + +#include "gp106/pmu_gp106.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -70,6 +76,7 @@ #include #include #include +#include static int gv11b_get_litter_value(struct gk20a *g, int value) { @@ -368,6 +375,30 @@ static const struct gpu_ops gv11b_ops = { .init_therm_setup_hw = gp10b_init_therm_setup_hw, .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, }, + .pmu = { + .pmu_setup_elpg = gp10b_pmu_setup_elpg, + .pmu_get_queue_head = pwr_pmu_queue_head_r, + .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, + .pmu_get_queue_tail = pwr_pmu_queue_tail_r, + .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, + .pmu_queue_head = gk20a_pmu_queue_head, + .pmu_queue_tail = gk20a_pmu_queue_tail, + .pmu_msgq_tail = gk20a_pmu_msgq_tail, + .pmu_mutex_size = pwr_pmu_mutex__size_1_v, + .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, + .pmu_mutex_release = gk20a_pmu_mutex_release, + .write_dmatrfbase = gp10b_write_dmatrfbase, + .pmu_elpg_statistics = gp106_pmu_elpg_statistics, + .pmu_pg_init_param = gv11b_pg_gr_init, + .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, + .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, + .dump_secure_fuses = pmu_dump_security_fuses_gp10b, + .reset_engine = gp106_pmu_engine_reset, + .is_engine_in_reset = gp106_pmu_is_engine_in_reset, + .pmu_nsbootstrap = gv11b_pmu_bootstrap, + .pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask, + .is_pmu_supported = gv11b_is_pmu_supported, + }, .regops = { .get_global_whitelist_ranges = gv11b_get_global_whitelist_ranges, @@ -463,6 +494,7 @@ int gv11b_init_hal(struct gk20a *g) gops->mm = gv11b_ops.mm; gops->fecs_trace = gv11b_ops.fecs_trace; gops->therm = gv11b_ops.therm; + gops->pmu = gv11b_ops.pmu; gops->regops = gv11b_ops.regops; gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; @@ -479,13 +511,44 @@ int gv11b_init_hal(struct gk20a *g) gv11b_ops.chip_init_gpu_characteristics; gops->get_litter_value = gv11b_ops.get_litter_value; - /* boot in non-secure modes for time beeing */ + /* boot in non-secure modes for time being */ __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false); __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); + /* priv security dependent ops */ + if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { + /* Add in ops from gm20b acr */ + gops->pmu.prepare_ucode = prepare_ucode_blob, + gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn, + gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap, + gops->pmu.is_priv_load = gm20b_is_priv_load, + gops->pmu.get_wpr = gm20b_wpr_info, + gops->pmu.alloc_blob_space = gm20b_alloc_blob_space, + gops->pmu.pmu_populate_loader_cfg = + gm20b_pmu_populate_loader_cfg, + gops->pmu.flcn_populate_bl_dmem_desc = + gm20b_flcn_populate_bl_dmem_desc, + gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt, + gops->pmu.falcon_clear_halt_interrupt_status = + clear_halt_interrupt_status, + gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1, + + gops->pmu.init_wpr_region = gm20b_pmu_init_acr; + gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; + gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; + gops->pmu.is_priv_load = gp10b_is_priv_load; + } else { + /* Inherit from gk20a */ + gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, + gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1, + + gops->pmu.load_lsfalcon_ucode = NULL; + gops->pmu.init_wpr_region = NULL; + gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; + } + gv11b_init_gr(g); - gv11b_init_pmu_ops(g); gv11b_init_uncompressed_kind_map(); gv11b_init_kind_attr(); -- cgit v1.2.2 From bcf556b640a3680522b03042574081abe0e17fef Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Tue, 8 Aug 2017 15:48:23 -0700 Subject: gpu: nvgpu: correct NUM_FBPAS Although igpu does not have an FBPA unit, the hardware reports one, and the ucode leaves space for one in the HWPM context save buffer. So let NUM_FBPAS reflect this, so that registers that follow this section in the context buffer are offset properly JIRA EVLR-1716 Change-Id: I067d5ec3afd356bcb4270fc2b5d12daef2ce3944 Signed-off-by: Peter Daifuku Reviewed-on: https://git-master.nvidia.com/r/1535274 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 521cafa3..4b64d44d 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -151,11 +151,14 @@ static int gv11b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_SM_PRI_STRIDE: ret = proj_sm_stride_v(); break; - /* GV11B does not have a FBPA unit, despite what's listed in the - * hw headers or read back through NV_PTOP_SCAL_NUM_FBPAS, - * so hardcode all values to 0. + /* Even though GV11B doesn't have an FBPA unit, the HW reports one, + * and the microcode as a result leaves space in the context buffer + * for one, so make sure SW accounts for this also. */ case GPU_LIT_NUM_FBPAS: + ret = proj_scal_litter_num_fbpas_v(); + break; + /* Hardcode FBPA values other than NUM_FBPAS to 0. */ case GPU_LIT_FBPA_STRIDE: case GPU_LIT_FBPA_BASE: case GPU_LIT_FBPA_SHARED_BASE: -- cgit v1.2.2 From 866165749a0b7b2e6b219bb26bffd69d790d97c5 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Thu, 17 Aug 2017 16:10:42 -0700 Subject: gpu: nvgpu: Reorg gr HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the gr sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I8feaa95a9830969221f7ac70a5ef61cdf25094c3 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1542988 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 153 +++++++++++++++++++++++++++++++++++- 1 file changed, 151 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 4b64d44d..0c5776f0 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -32,6 +32,7 @@ #include "gk20a/regops_gk20a.h" #include "gk20a/fb_gk20a.h" #include "gk20a/pmu_gk20a.h" +#include "gk20a/gr_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" @@ -51,6 +52,7 @@ #include "gp10b/fb_gp10b.h" #include "gp10b/mm_gp10b.h" #include "gp10b/pmu_gp10b.h" +#include "gp10b/gr_gp10b.h" #include "gp106/pmu_gp106.h" @@ -194,6 +196,150 @@ static const struct gpu_ops gv11b_ops = { .isr_nonstall = gp10b_ce_nonstall_isr, .get_num_pce = gv11b_ce_get_num_pce, }, + .gr = { + .init_gpc_mmu = gr_gv11b_init_gpc_mmu, + .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults, + .cb_size_default = gr_gv11b_cb_size_default, + .calc_global_ctx_buffer_size = + gr_gv11b_calc_global_ctx_buffer_size, + .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb, + .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, + .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, + .commit_global_pagepool = gr_gp10b_commit_global_pagepool, + .handle_sw_method = gr_gv11b_handle_sw_method, + .set_alpha_circular_buffer_size = + gr_gv11b_set_alpha_circular_buffer_size, + .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size, + .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions, + .is_valid_class = gr_gv11b_is_valid_class, + .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class, + .is_valid_compute_class = gr_gv11b_is_valid_compute_class, + .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, + .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, + .init_fs_state = gr_gv11b_init_fs_state, + .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, + .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, + .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, + .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask, + .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, + .free_channel_ctx = gk20a_free_channel_ctx, + .alloc_obj_ctx = gk20a_alloc_obj_ctx, + .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull, + .get_zcull_info = gr_gk20a_get_zcull_info, + .is_tpc_addr = gr_gm20b_is_tpc_addr, + .get_tpc_num = gr_gm20b_get_tpc_num, + .detect_sm_arch = gr_gv11b_detect_sm_arch, + .add_zbc_color = gr_gp10b_add_zbc_color, + .add_zbc_depth = gr_gp10b_add_zbc_depth, + .zbc_set_table = gk20a_gr_zbc_set_table, + .zbc_query_table = gr_gk20a_query_zbc, + .pmu_save_zbc = gk20a_pmu_save_zbc, + .add_zbc = gr_gk20a_add_zbc, + .pagepool_default_size = gr_gv11b_pagepool_default_size, + .init_ctx_state = gr_gp10b_init_ctx_state, + .alloc_gr_ctx = gr_gp10b_alloc_gr_ctx, + .free_gr_ctx = gr_gp10b_free_gr_ctx, + .update_ctxsw_preemption_mode = + gr_gp10b_update_ctxsw_preemption_mode, + .dump_gr_regs = gr_gv11b_dump_gr_status_regs, + .update_pc_sampling = gr_gm20b_update_pc_sampling, + .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask, + .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp, + .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc, + .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask, + .get_max_fbps_count = gr_gm20b_get_max_fbps_count, + .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, + .wait_empty = gr_gv11b_wait_empty, + .init_cyclestats = gr_gv11b_init_cyclestats, + .set_sm_debug_mode = gv11b_gr_set_sm_debug_mode, + .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, + .bpt_reg_info = gv11b_gr_bpt_reg_info, + .get_access_map = gr_gv11b_get_access_map, + .handle_fecs_error = gr_gv11b_handle_fecs_error, + .handle_sm_exception = gr_gk20a_handle_sm_exception, + .handle_tex_exception = gr_gv11b_handle_tex_exception, + .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions, + .enable_exceptions = gr_gv11b_enable_exceptions, + .get_lrf_tex_ltc_dram_override = get_ecc_override_val, + .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, + .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, + .record_sm_error_state = gv11b_gr_record_sm_error_state, + .update_sm_error_state = gv11b_gr_update_sm_error_state, + .clear_sm_error_state = gm20b_gr_clear_sm_error_state, + .suspend_contexts = gr_gp10b_suspend_contexts, + .resume_contexts = gr_gk20a_resume_contexts, + .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, + .fuse_override = gp10b_gr_fuse_override, + .init_sm_id_table = gr_gv11b_init_sm_id_table, + .load_smid_config = gr_gv11b_load_smid_config, + .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, + .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, + .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr, + .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr, + .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr, + .setup_rop_mapping = gr_gv11b_setup_rop_mapping, + .program_zcull_mapping = gr_gv11b_program_zcull_mapping, + .commit_global_timeslice = gr_gv11b_commit_global_timeslice, + .commit_inst = gr_gv11b_commit_inst, + .write_zcull_ptr = gr_gv11b_write_zcull_ptr, + .write_pm_ptr = gr_gv11b_write_pm_ptr, + .init_elcg_mode = gr_gv11b_init_elcg_mode, + .load_tpc_mask = gr_gv11b_load_tpc_mask, + .inval_icache = gr_gk20a_inval_icache, + .trigger_suspend = gv11b_gr_sm_trigger_suspend, + .wait_for_pause = gr_gk20a_wait_for_pause, + .resume_from_pause = gv11b_gr_resume_from_pause, + .clear_sm_errors = gr_gk20a_clear_sm_errors, + .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, + .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel, + .sm_debugger_attached = gv11b_gr_sm_debugger_attached, + .suspend_single_sm = gv11b_gr_suspend_single_sm, + .suspend_all_sms = gv11b_gr_suspend_all_sms, + .resume_single_sm = gv11b_gr_resume_single_sm, + .resume_all_sms = gv11b_gr_resume_all_sms, + .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr, + .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr, + .get_sm_no_lock_down_hww_global_esr_mask = + gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask, + .lock_down_sm = gv11b_gr_lock_down_sm, + .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down, + .clear_sm_hww = gv11b_gr_clear_sm_hww, + .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, + .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, + .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, + .set_boosted_ctx = gr_gp10b_set_boosted_ctx, + .set_preemption_mode = gr_gp10b_set_preemption_mode, + .set_czf_bypass = NULL, + .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception, + .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va, + .init_preemption_state = NULL, + .update_boosted_ctx = gr_gp10b_update_boosted_ctx, + .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, + .create_gr_sysfs = gr_gv11b_create_sysfs, + .set_ctxsw_preemption_mode = gr_gp10b_set_ctxsw_preemption_mode, + .is_etpc_addr = gv11b_gr_pri_is_etpc_addr, + .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table, + .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, + .zbc_s_query_table = gr_gv11b_zbc_s_query_table, + .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl, + .restore_context_header = gv11b_restore_context_header, + .handle_gpc_gpcmmu_exception = + gr_gv11b_handle_gpc_gpcmmu_exception, + .add_zbc_type_s = gr_gv11b_add_zbc_type_s, + .get_egpc_base = gv11b_gr_get_egpc_base, + .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num, + .handle_gpc_gpccs_exception = + gr_gv11b_handle_gpc_gpccs_exception, + .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl, + .access_smpc_reg = gv11b_gr_access_smpc_reg, + .is_egpc_addr = gv11b_gr_pri_is_egpc_addr, + .add_zbc_s = gr_gv11b_add_zbc_stencil, + .handle_gcc_exception = gr_gv11b_handle_gcc_exception, + .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle, + .handle_tpc_sm_ecc_exception = + gr_gv11b_handle_tpc_sm_ecc_exception, + .decode_egpc_addr = gv11b_gr_decode_egpc_addr, + }, .fb = { .reset = gv11b_fb_reset, .init_hw = gk20a_fb_init_hw, @@ -490,6 +636,7 @@ int gv11b_init_hal(struct gk20a *g) gops->ltc = gv11b_ops.ltc; gops->ce2 = gv11b_ops.ce2; + gops->gr = gv11b_ops.gr; gops->fb = gv11b_ops.fb; gops->clock_gating = gv11b_ops.clock_gating; gops->fifo = gv11b_ops.fifo; @@ -541,6 +688,8 @@ int gv11b_init_hal(struct gk20a *g) gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; gops->pmu.is_priv_load = gp10b_is_priv_load; + + gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; } else { /* Inherit from gk20a */ gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, @@ -549,9 +698,9 @@ int gv11b_init_hal(struct gk20a *g) gops->pmu.load_lsfalcon_ucode = NULL; gops->pmu.init_wpr_region = NULL; gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; - } - gv11b_init_gr(g); + gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; + } gv11b_init_uncompressed_kind_map(); gv11b_init_kind_attr(); -- cgit v1.2.2 From c094ea161785a8c00bb2dc8c55e1a2bb8ffbcfc7 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Wed, 30 Aug 2017 15:03:25 +0530 Subject: gpu: nvgpu: gv11b: Secure boot support. This patch adds Secure boot support for T194. JIRA GPUT19X-5 Change-Id: If78e5e0ecfa58bcac132716c7f2c155f21899027 Signed-off-by: Deepak Goyal Reviewed-on: https://git-master.nvidia.com/r/1514558 Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 36 ++++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 12 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 0c5776f0..c6c8e18c 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -55,6 +55,7 @@ #include "gp10b/gr_gp10b.h" #include "gp106/pmu_gp106.h" +#include "gp106/acr_gp106.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -65,6 +66,7 @@ #include "gr_ctx_gv11b.h" #include "mm_gv11b.h" #include "pmu_gv11b.h" +#include "acr_gv11b.h" #include "fb_gv11b.h" #include "fifo_gv11b.h" #include "gv11b_gating_reglist.h" @@ -79,6 +81,7 @@ #include #include #include +#include static int gv11b_get_litter_value(struct gk20a *g, int value) { @@ -633,6 +636,8 @@ int gv11b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + u32 val; + bool priv_security; gops->ltc = gv11b_ops.ltc; gops->ce2 = gv11b_ops.ce2; @@ -661,33 +666,38 @@ int gv11b_init_hal(struct gk20a *g) gv11b_ops.chip_init_gpu_characteristics; gops->get_litter_value = gv11b_ops.get_litter_value; - /* boot in non-secure modes for time being */ + val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); + if (val) { + priv_security = true; + pr_err("priv security is enabled\n"); + } else { + priv_security = false; + pr_err("priv security is disabled\n"); + } __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false); - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, priv_security); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, priv_security); /* priv security dependent ops */ if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { /* Add in ops from gm20b acr */ - gops->pmu.prepare_ucode = prepare_ucode_blob, - gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn, - gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap, - gops->pmu.is_priv_load = gm20b_is_priv_load, + gops->pmu.prepare_ucode = gp106_prepare_ucode_blob, + gops->pmu.pmu_setup_hw_and_bootstrap = gv11b_bootstrap_hs_flcn, gops->pmu.get_wpr = gm20b_wpr_info, gops->pmu.alloc_blob_space = gm20b_alloc_blob_space, gops->pmu.pmu_populate_loader_cfg = - gm20b_pmu_populate_loader_cfg, + gp106_pmu_populate_loader_cfg, gops->pmu.flcn_populate_bl_dmem_desc = - gm20b_flcn_populate_bl_dmem_desc, + gp106_flcn_populate_bl_dmem_desc, gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt, gops->pmu.falcon_clear_halt_interrupt_status = clear_halt_interrupt_status, - gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1, + gops->pmu.init_falcon_setup_hw = gv11b_init_pmu_setup_hw1, gops->pmu.init_wpr_region = gm20b_pmu_init_acr; gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; - gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; - gops->pmu.is_priv_load = gp10b_is_priv_load; + gops->pmu.is_lazy_bootstrap = gv11b_is_lazy_bootstrap, + gops->pmu.is_priv_load = gv11b_is_priv_load, gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; } else { @@ -702,8 +712,10 @@ int gv11b_init_hal(struct gk20a *g) gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; } + __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); gv11b_init_uncompressed_kind_map(); gv11b_init_kind_attr(); + g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; g->name = "gv11b"; -- cgit v1.2.2 From 91a85229996e80a4125a8661f24b1446f4020c83 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Fri, 8 Sep 2017 19:18:30 +0530 Subject: gpu: nvgpu: gv11b: add ops for getting timestamp. assign GPU bus ops for getting timestamps using PTIMER. BUG 1957272 Change-Id: I1ded165858849a6a93e6ae0617ec1423d48f75ed Signed-off-by: Deepak Goyal Reviewed-on: https://git-master.nvidia.com/r/1555528 Reviewed-by: svc-mobile-coverity Reviewed-by: Seshendra Gadagottu Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index c6c8e18c..e9053081 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -73,6 +73,7 @@ #include "regops_gv11b.h" #include "subctx_gv11b.h" +#include #include #include @@ -610,6 +611,7 @@ static const struct gpu_ops gv11b_ops = { .init_hw = gk20a_bus_init_hw, .isr = gk20a_bus_isr, .read_ptimer = gk20a_read_ptimer, + .get_timestamps_zipper = nvgpu_get_timestamps_zipper, .bar1_bind = NULL, }, #if defined(CONFIG_GK20A_CYCLE_STATS) -- cgit v1.2.2 From 52f50addc6cedf57fc3d8ff06314921499fb59e3 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 13 Sep 2017 17:35:03 +0530 Subject: gpu: nvgpu: add TSG enable/disable operations Add TSG enable/disable operations for gv11b/gv100 To disable a TSG we continue to use gk20a_disable_tsg() To enable a TSG add new API gv11b_fifo_enable_tsg() since TSG enable sequence is different for Volta than previous versions For Volta it is sufficient to loop over all the channels in TSG and enable them sequentially Bug 1739362 Change-Id: Id4b4684959204c6101ceda83487a41fbfcba8b5f Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1560642 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index e9053081..947ac503 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -430,6 +430,8 @@ static const struct gpu_ops gv11b_ops = { .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, .preempt_channel = gv11b_fifo_preempt_channel, .preempt_tsg = gv11b_fifo_preempt_tsg, + .enable_tsg = gv11b_fifo_enable_tsg, + .disable_tsg = gk20a_disable_tsg, .update_runlist = gk20a_fifo_update_runlist, .trigger_mmu_fault = NULL, .get_mmu_fault_info = NULL, -- cgit v1.2.2 From f720b309f1ea87a301bcb216983396f3d9c55abc Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 14 Sep 2017 05:48:07 -0700 Subject: gpu: nvgpu: add tsg_verify_status_faulted operation Add new API gv11b_fifo_tsg_verify_status_faulted() and use that as g->ops.fifo.tsg_verify_status_faulted operation for gv11b/gv100 This API will check if channel has ENG_FAULTED status set, if yes it will clear CE method buffer in case saved out channel is same as faulted channel We need to write 0 to method count to invalidate CE method buffer Also set g->ops.fifo.tsg_verify_status_ctx_reload operation for gv11b/gv100 Bug 200327095 Change-Id: I9d2b0f13faf881b30680219bbcadfd4969c4dff6 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1560643 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 947ac503..fcc3b91a 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -432,6 +432,8 @@ static const struct gpu_ops gv11b_ops = { .preempt_tsg = gv11b_fifo_preempt_tsg, .enable_tsg = gv11b_fifo_enable_tsg, .disable_tsg = gk20a_disable_tsg, + .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, + .tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted, .update_runlist = gk20a_fifo_update_runlist, .trigger_mmu_fault = NULL, .get_mmu_fault_info = NULL, -- cgit v1.2.2 From 1c850d0beef16216c21b3c833a5d3333ef229788 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 12 Sep 2017 13:29:59 -0700 Subject: gpu: nvgpu: gv11b: fecs_trace ops are set to NULL CTXSW_TRACE will be enabled only after it is verified. Set all function pointers for fecs_trace to NULL JIRA GPUT19X-42 Change-Id: I7a807f997f683c19541e55fa7e3d5d3ff6b645d2 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1558464 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index fcc3b91a..2abd6243 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -487,20 +487,20 @@ static const struct gpu_ops gv11b_ops = { }, #ifdef CONFIG_GK20A_CTXSW_TRACE .fecs_trace = { - .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc, - .free_user_buffer = gk20a_ctxsw_dev_ring_free, - .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer, - .init = gk20a_fecs_trace_init, - .deinit = gk20a_fecs_trace_deinit, - .enable = gk20a_fecs_trace_enable, - .disable = gk20a_fecs_trace_disable, - .is_enabled = gk20a_fecs_trace_is_enabled, - .reset = gk20a_fecs_trace_reset, - .flush = gp10b_fecs_trace_flush, - .poll = gk20a_fecs_trace_poll, - .bind_channel = gk20a_fecs_trace_bind_channel, - .unbind_channel = gk20a_fecs_trace_unbind_channel, - .max_entries = gk20a_gr_max_entries, + .alloc_user_buffer = NULL, + .free_user_buffer = NULL, + .mmap_user_buffer = NULL, + .init = NULL, + .deinit = NULL, + .enable = NULL, + .disable = NULL, + .is_enabled = NULL, + .reset = NULL, + .flush = NULL, + .poll = NULL, + .bind_channel = NULL, + .unbind_channel = NULL, + .max_entries = NULL, }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ .mm = { -- cgit v1.2.2 From 0420dd383e9aca0c764ad88979f88292603198d9 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 18 Sep 2017 11:17:15 -0700 Subject: gpu: nvgpu: gv11b: Initialize ctxsw hdr counters Initlize following context switch header counters for gv11b: ctxsw_prog_main_image_num_save_ops ctxsw_prog_main_image_num_restore_ops ctxsw_prog_main_image_num_wfi_save_ops ctxsw_prog_main_image_num_cta_save_ops ctxsw_prog_main_image_num_gfxp_save_ops ctxsw_prog_main_image_num_cilp_save_ops Reused gp10b gr hal function gr_gp10b_init_ctxsw_hdr_data() for this. Bug 1958308 Signed-off-by: seshendra Gadagottu Change-Id: I10d83e35ccd8cba517ebaba1f0e5bec5a0f68ba5 Reviewed-on: https://git-master.nvidia.com/r/1562655 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 2abd6243..be3f2456 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -343,6 +343,7 @@ static const struct gpu_ops gv11b_ops = { .handle_tpc_sm_ecc_exception = gr_gv11b_handle_tpc_sm_ecc_exception, .decode_egpc_addr = gv11b_gr_decode_egpc_addr, + .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data, }, .fb = { .reset = gv11b_fb_reset, -- cgit v1.2.2 From a24382d09788ffc8f8688a473a38d37df589b131 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 20 Sep 2017 22:34:54 +0530 Subject: gpu: nvgpu: Add support for WPR info read from FB update .read_wpr_info HAL of gv11b & gv100 to point to gm20b_fb_read_wpr_info() JIRA NVGPU-128 Change-Id: I5ece4c72dbe0f9e7827888e2a15d8b7dda6fcb42 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1564684 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index be3f2456..09825b98 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -357,6 +357,7 @@ static const struct gpu_ops gv11b_ops = { .compressible_page_size = gp10b_fb_compressible_page_size, .vpr_info_fetch = gm20b_fb_vpr_info_fetch, .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .read_wpr_info = gm20b_fb_read_wpr_info, .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .set_debug_mode = gm20b_fb_set_debug_mode, .tlb_invalidate = gk20a_fb_tlb_invalidate, -- cgit v1.2.2 From d61643c0200983dc340d37962bb0a3ca900a3e97 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 25 Sep 2017 08:59:28 -0700 Subject: gpu: nvgpu: gv11b: Change license for common files to MIT Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity Reviewed-by: David Martinez Nieto Reviewed-by: Seshendra Gadagottu Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 09825b98..f8bdc213 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include -- cgit v1.2.2 From 9825a8ec69d54c725c38015006aed655d10ac567 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 15 Aug 2017 15:28:35 -0700 Subject: gpu: nvgpu: fix handling of EGPC_ETPC_SM addresses Implemented litter values for following defines: GPU_LIT_SMPC_PRI_BASE GPU_LIT_SMPC_PRI_SHARED_BASE GPU_LIT_SMPC_PRI_UNIQUE_BASE9 GPU_LIT_SMPC_PRI_STRIDE Added broadcast flags for smpc Handled all combinations of broadcast/unicast EGPC, ETPC, SM Bug 200337994 Change-Id: I7aa3c4d9ac4e819010061d44fb5a40056762f518 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1539075 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index f8bdc213..9baa3581 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -166,6 +166,18 @@ static int gv11b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_SM_PRI_STRIDE: ret = proj_sm_stride_v(); break; + case GPU_LIT_SMPC_PRI_BASE: + ret = proj_smpc_base_v(); + break; + case GPU_LIT_SMPC_PRI_SHARED_BASE: + ret = proj_smpc_shared_base_v(); + break; + case GPU_LIT_SMPC_PRI_UNIQUE_BASE: + ret = proj_smpc_unique_base_v(); + break; + case GPU_LIT_SMPC_PRI_STRIDE: + ret = proj_smpc_stride_v(); + break; /* Even though GV11B doesn't have an FBPA unit, the HW reports one, * and the microcode as a result leaves space in the context buffer * for one, so make sure SW accounts for this also. -- cgit v1.2.2 From f63f96866dd3cd696e37cf7e83d419cca4f965fa Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 28 Sep 2017 16:57:16 -0700 Subject: gpu: nvgpu: gv11b: init therm regs for pwr/clk init *eng_delay*, *eng_idle_filt*, *fecs_idle_filter* and *hubmmu_idle_filter* in therm regs. Change-Id: I4ab5374084e993cd96ef28ace87b6013b996178d Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1570556 Reviewed-by: Terje Bergstrom Reviewed-by: Seshendra Gadagottu Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 9baa3581..f2fb9972 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -81,6 +81,7 @@ #include "gv11b_gating_reglist.h" #include "regops_gv11b.h" #include "subctx_gv11b.h" +#include "therm_gv11b.h" #include #include @@ -553,7 +554,7 @@ static const struct gpu_ops gv11b_ops = { }, .therm = { .init_therm_setup_hw = gp10b_init_therm_setup_hw, - .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, + .elcg_init_idle_filters = gv11b_elcg_init_idle_filters, }, .pmu = { .pmu_setup_elpg = gp10b_pmu_setup_elpg, -- cgit v1.2.2 From dc5edb1417390b583b5ff2406e554ce0770e02ae Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Wed, 16 Aug 2017 16:13:18 -0700 Subject: gpu: nvgpu: rename ops.mm.get_physical_addr_bits T19x/gv100 version of same patch in kernel/nvgpu. Change-Id: I7174864cf1e072af61609c0843da16fcafe54c02 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1566750 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index f2fb9972..0c509ee2 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -540,7 +540,7 @@ static const struct gpu_ops gv11b_ops = { .get_big_page_sizes = gm20b_mm_get_big_page_sizes, .get_default_big_page_size = gp10b_mm_get_default_big_page_size, .gpu_phys_addr = gv11b_gpu_phys_addr, - .get_physical_addr_bits = gp10b_mm_get_physical_addr_bits, + .get_iommu_bit = gp10b_mm_get_iommu_bit, .get_mmu_levels = gp10b_mm_get_mmu_levels, .init_pdb = gp10b_mm_init_pdb, .init_mm_setup_hw = gv11b_init_mm_setup_hw, -- cgit v1.2.2 From 19d602da31f81d9dc89a42b2bc84ce14a300773b Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 3 Oct 2017 14:01:51 +0530 Subject: gpu: nvgpu: verify channel status while closing per-platform We right now call gk20a_fifo_tsg_unbind_channel_verify_status() to verify channel status while unbinding a channel from TSG while closing Add support to do this verification per-platform and keep this disabled for vgpu platforms Bug 200327095 Change-Id: I6e2a6a09c784d24ac49477d5450b7d4b671878e3 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1572369 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 0c509ee2..f366a90e 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -456,6 +456,7 @@ static const struct gpu_ops gv11b_ops = { .preempt_tsg = gv11b_fifo_preempt_tsg, .enable_tsg = gv11b_fifo_enable_tsg, .disable_tsg = gk20a_disable_tsg, + .tsg_verify_channel_status = gk20a_fifo_tsg_unbind_channel_verify_status, .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, .tsg_verify_status_faulted = gv11b_fifo_tsg_verify_status_faulted, .update_runlist = gk20a_fifo_update_runlist, -- cgit v1.2.2 From bb1c38e2f5f133a4281f73f8076a206ec728bd22 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 6 Oct 2017 10:36:49 -0700 Subject: gpu: nvgpu: gv11b: perfbuffer enable and disable dbg ops set to NULL Will be enabled after feature is verified on volta Bug 200352825 Change-Id: Idbe318ea82051e53f15caecf2afb15d72b99acea Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1574482 Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index f366a90e..4a289d8f 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -633,8 +633,8 @@ static const struct gpu_ops gv11b_ops = { nvgpu_check_and_set_context_reservation, .release_profiler_reservation = nvgpu_release_profiler_reservation, - .perfbuffer_enable = gk20a_perfbuf_enable_locked, - .perfbuffer_disable = gk20a_perfbuf_disable_locked, + .perfbuffer_enable = NULL, + .perfbuffer_disable = NULL, }, .bus = { .init_hw = gk20a_bus_init_hw, -- cgit v1.2.2 From 4b8dc71de5696679f13f8863bc5775a23e786b34 Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Fri, 6 Oct 2017 15:38:11 -0700 Subject: gpu: nvgpu: vgpu: flatten out t19x vgpu hal Instead of calling the native HAL init function then adding multiple layers of modification for VGPU, flatten out the sequence so that all entry points are set statically and visible in a single file. JIRA ESRM-30 Change-Id: I8d277aaccb0e63b2d504e7aba32eb31ef82f4ec0 Signed-off-by: Peter Daifuku Reviewed-on: https://git-master.nvidia.com/r/1574619 Reviewed-by: svc-mobile-coverity Reviewed-by: Richard Zhao GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 4a289d8f..4241145a 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -94,7 +94,7 @@ #include #include -static int gv11b_get_litter_value(struct gk20a *g, int value) +int gv11b_get_litter_value(struct gk20a *g, int value) { int ret = EINVAL; switch (value) { -- cgit v1.2.2 From 201ccbfa8503daee9562a22f50a5b626fe4cc6a1 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 16 Oct 2017 12:14:29 -0700 Subject: gpu: nvgpu: gv11b: update dbg ops Updated following hal functions for gv11b and reused them for gv100: perfbuffer_enable perfbuffer_disable These changes are needed because of following reasons: 1. Register offsets for perf_pmasys_* are changed for gv11b/gv100 from gk20a. 2. Updated memory type for perf_pmasys_mem_block_target to sys_ncoh_f(). Bug 200327596 Change-Id: Ia672ac561917c8ed36caea9cc7e74b7fc7ce8188 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1571074 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 4241145a..e7e2be54 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -66,6 +66,7 @@ #include "gp106/pmu_gp106.h" #include "gp106/acr_gp106.h" +#include "dbg_gpu_gv11b.h" #include "hal_gv11b.h" #include "gr_gv11b.h" #include "mc_gv11b.h" @@ -633,8 +634,8 @@ static const struct gpu_ops gv11b_ops = { nvgpu_check_and_set_context_reservation, .release_profiler_reservation = nvgpu_release_profiler_reservation, - .perfbuffer_enable = NULL, - .perfbuffer_disable = NULL, + .perfbuffer_enable = gv11b_perfbuf_enable_locked, + .perfbuffer_disable = gv11b_perfbuf_disable_locked, }, .bus = { .init_hw = gk20a_bus_init_hw, -- cgit v1.2.2 From 62e133029d5a89e07e3ba5e96475c0960c0bc3dd Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Mon, 16 Oct 2017 12:38:46 -0700 Subject: gpu: nvgpu: Refactoring nvgpu_vm functions Change required for equivalent change on nvgpu. This is required since a few HALs were added that must be populated for all chips. This patch adds those HAL definitions for gv11b, gv100, and the vgpu. JIRA NVGPU-30 JIRA NVGPU-138 Change-Id: I65374764350a5cacce8624b15d98947fada35a4a Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1579865 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index e7e2be54..328398d9 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -549,6 +549,8 @@ static const struct gpu_ops gv11b_ops = { .is_bar1_supported = gv11b_mm_is_bar1_supported, .init_inst_block = gv11b_init_inst_block, .mmu_fault_pending = gv11b_mm_mmu_fault_pending, + .get_kind_invalid = gm20b_get_kind_invalid, + .get_kind_pitch = gm20b_get_kind_pitch, .init_bar2_vm = gb10b_init_bar2_vm, .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, .remove_bar2_vm = gv11b_mm_remove_bar2_vm, -- cgit v1.2.2 From 387ecf8a6360f463a129ab569aaef921fe0a2b0e Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 18 Oct 2017 11:40:46 -0700 Subject: gpu: nvgpu: gv1xx: Remove HAL for restore_context_header gr restore_context_header is not required any more after enabling per context va mode for subcontext. Cleaning-up unused function pointers from gv100 and gv11b HAL. Change-Id: I65cc7d12d3c96726d323defd99726c3e259e7e63 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1581432 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 328398d9..168def5c 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -349,7 +349,6 @@ static const struct gpu_ops gv11b_ops = { .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, .zbc_s_query_table = gr_gv11b_zbc_s_query_table, .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl, - .restore_context_header = gv11b_restore_context_header, .handle_gpc_gpcmmu_exception = gr_gv11b_handle_gpc_gpcmmu_exception, .add_zbc_type_s = gr_gv11b_add_zbc_type_s, -- cgit v1.2.2 From cf70c925cd3d8e6c83feee04316b080d5f258afc Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 22 Jun 2017 16:28:19 -0700 Subject: gpu: nvgpu: gv11b: update css ops Updated following hal functions for css gv11b and reused them for gv100: enable_snapshot disable_snapshot check_data_available These changes are needed because of following reasons: 1. Register offsets for perf_pmasys_* are changed for gv11b/gv100 from gk20a. 2. Updated memory type for perf_pmasys_mem_block_target based on memory aperture used for hwpm inst_block. Bug 200327596 Change-Id: I500d17670e2f389d8d0e77884374bcc3504a41f8 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1507546 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 168def5c..22beabf7 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -68,6 +68,7 @@ #include "dbg_gpu_gv11b.h" #include "hal_gv11b.h" +#include "css_gr_gv11b.h" #include "gr_gv11b.h" #include "mc_gv11b.h" #include "ltc_gv11b.h" @@ -647,9 +648,9 @@ static const struct gpu_ops gv11b_ops = { }, #if defined(CONFIG_GK20A_CYCLE_STATS) .css = { - .enable_snapshot = css_hw_enable_snapshot, - .disable_snapshot = css_hw_disable_snapshot, - .check_data_available = css_hw_check_data_available, + .enable_snapshot = gv11b_css_hw_enable_snapshot, + .disable_snapshot = gv11b_css_hw_disable_snapshot, + .check_data_available = gv11b_css_hw_check_data_available, .set_handled_snapshots = css_hw_set_handled_snapshots, .allocate_perfmon_ids = css_gr_allocate_perfmon_ids, .release_perfmon_ids = css_gr_release_perfmon_ids, -- cgit v1.2.2 From 2904e3ac0081d4e898378f6ba667658c85547368 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 4 Oct 2017 19:41:04 +0530 Subject: gpu: nvgpu: gv100 memory unlock support - Added method to load mem unlock binary into nvdec falcon & execute to perform mem unlock if VPR enabled. - Updated .mem_unlock gv100 HAL to point method gv100_fb_memory_unlock(). - Updated .mem_unlock gv11b HAL to NULL. - Added vpr info hw registers - Added nvdec enable hw register Change-Id: Ia4bf820ae103baede679d300d1d390fd748c919a Signed-off-by: Mahantesh Kumbar (cherry picked from commit 2e176ad9d47316bf4d001692a2ae07e6c1fb1ccb) Reviewed-on: https://git-master.nvidia.com/r/1573101 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 22beabf7..729727c9 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -385,6 +385,7 @@ static const struct gpu_ops gv11b_ops = { .set_debug_mode = gm20b_fb_set_debug_mode, .tlb_invalidate = gk20a_fb_tlb_invalidate, .hub_isr = gv11b_fb_hub_isr, + .mem_unlock = NULL, }, .clock_gating = { .slcg_bus_load_gating_prod = -- cgit v1.2.2 From 6114553413297dbcae637bc50ef2ff2a6c0858d1 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 19 Oct 2017 10:12:24 -0700 Subject: gpu: nvgpu: gv100: fix timeout handling GV100 has a larger vidmem size and a slower sideband to sysmem so timeouts need to be adjusted to avoid false positives. JIRA: NVGPUGV100-36 Change-Id: I3cbc19aa1158c89bc48ae1fa6ec4bc755cd9389d Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1582092 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 729727c9..5b10b7d2 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -438,6 +438,7 @@ static const struct gpu_ops gv11b_ops = { gr_gv11b_pg_gr_load_gating_prod, }, .fifo = { + .get_preempt_timeout = gv11b_fifo_get_preempt_timeout, .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, .bind_channel = channel_gm20b_bind, .unbind_channel = channel_gv11b_unbind, -- cgit v1.2.2 From 0899e11d4bb630381607a0c245f72476e2e9209e Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Fri, 6 Oct 2017 17:20:12 -0700 Subject: gpu: nvgpu: Cleanup generic MM code t19x changes necessary for change in core MM code. JIRA NVGPU-30 Change-Id: I62f419450c1a33d0826390d7cbb5ad93569f8c89 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1577265 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 5b10b7d2..46323cf9 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -549,6 +549,7 @@ static const struct gpu_ops gv11b_ops = { .init_pdb = gp10b_mm_init_pdb, .init_mm_setup_hw = gv11b_init_mm_setup_hw, .is_bar1_supported = gv11b_mm_is_bar1_supported, + .alloc_inst_block = gk20a_alloc_inst_block, .init_inst_block = gv11b_init_inst_block, .mmu_fault_pending = gv11b_mm_mmu_fault_pending, .get_kind_invalid = gm20b_get_kind_invalid, -- cgit v1.2.2 From c6ccb5f2a1e9a8999436f6c28ed5c416c5418ae3 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 23 Oct 2017 10:20:12 -0700 Subject: gpu: nvgpu: gv11b: use scg perf for smid numbering For SCG to work, smid numbering needs to be done based on scg performance of tpcs. For gv11b and gv11b vgpu, reuse gv100 function "gr_gv100_init_sm_id_table" to do this. Used local variable "index" to avoid multiple computations in the function: gr_gv100_init_sm_id_table index = sm_id + sm Add deug info for printing initialized gpc/tpc/sm/global_tpc indexs. Bug 1842197 Change-Id: Ibf10f47f10a8ca58b86c307a22e159b2cc0d0f43 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1583916 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 46323cf9..8e4cdab8 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -66,6 +66,8 @@ #include "gp106/pmu_gp106.h" #include "gp106/acr_gp106.h" +#include "gv100/gr_gv100.h" + #include "dbg_gpu_gv11b.h" #include "hal_gv11b.h" #include "css_gr_gv11b.h" @@ -298,7 +300,7 @@ static const struct gpu_ops gv11b_ops = { .resume_contexts = gr_gk20a_resume_contexts, .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, .fuse_override = gp10b_gr_fuse_override, - .init_sm_id_table = gr_gv11b_init_sm_id_table, + .init_sm_id_table = gr_gv100_init_sm_id_table, .load_smid_config = gr_gv11b_load_smid_config, .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, -- cgit v1.2.2 From 1cbb5ea0235f15180b1d4299499cab85db23c5ce Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Fri, 13 Oct 2017 17:15:46 -0700 Subject: gpu: nvgpu: init_cyclestats fixes - in the native case, replace calls for init_cyclestats with the gm20b version, as each chip had identical versions of the code. - in the virtual case, use the vgpu version of the function in order to get the new max_css_buffer_size characteristic set to the mempool size. JIRA ESRM-54 Bug 200296210 Change-Id: I475876cb392978fb1350ede58e37d0962ae095c3 Signed-off-by: Peter Daifuku Reviewed-on: https://git-master.nvidia.com/r/1578934 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 8e4cdab8..400c2ad0 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -280,7 +280,7 @@ static const struct gpu_ops gv11b_ops = { .get_max_fbps_count = gr_gm20b_get_max_fbps_count, .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, .wait_empty = gr_gv11b_wait_empty, - .init_cyclestats = gr_gv11b_init_cyclestats, + .init_cyclestats = gr_gm20b_init_cyclestats, .set_sm_debug_mode = gv11b_gr_set_sm_debug_mode, .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, .bpt_reg_info = gv11b_gr_bpt_reg_info, -- cgit v1.2.2 From 20294264468eecc8c1a065aa83d5f1b46ff07e7e Mon Sep 17 00:00:00 2001 From: David Nieto Date: Mon, 23 Oct 2017 14:01:28 -0700 Subject: gpu: nvgpu: gv1xx: resize patch buffer Follow the sizing consideration in bug 1753763 to support dynamic TPC modes and subcontexts. bug 200350539 Change-Id: Ibbdbf02f9c2ea3f082c1b2810ae7176b0775d461 Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1584034 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 400c2ad0..4de9786b 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -227,6 +227,7 @@ static const struct gpu_ops gv11b_ops = { .get_num_pce = gv11b_ce_get_num_pce, }, .gr = { + .get_patch_slots = gr_gv100_get_patch_slots, .init_gpc_mmu = gr_gv11b_init_gpc_mmu, .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults, .cb_size_default = gr_gv11b_cb_size_default, -- cgit v1.2.2 From afd1649cfcae97e873663586d55f9a4cfd671808 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 26 Oct 2017 15:20:39 -0700 Subject: gpu: nvgpu: Move ctxsw_trace_gk20a.c to common/linux Fixups for the change of name subject in nvgpu. JIRA NVGPU-287 Change-Id: I6c19733079061a42786b94fc48db374d715ccbef Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1586548 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 4de9786b..39f9572c 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -687,7 +687,9 @@ int gv11b_init_hal(struct gk20a *g) gops->fifo = gv11b_ops.fifo; gops->gr_ctx = gv11b_ops.gr_ctx; gops->mm = gv11b_ops.mm; +#ifdef CONFIG_GK20A_CTXSW_TRACE gops->fecs_trace = gv11b_ops.fecs_trace; +#endif gops->therm = gv11b_ops.therm; gops->pmu = gv11b_ops.pmu; gops->regops = gv11b_ops.regops; -- cgit v1.2.2 From f472922b3582dbba78b633958a4cb7b65ddb3f03 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Tue, 31 Oct 2017 12:23:30 -0700 Subject: gpu: nvgpu: Split ctxsw_trace API into non-Linux component T19x component for similar change in the main nvgpu code. JIRA NVGPU-287 Change-Id: Ib126b3d1fb562850fbb3ab89103f2a7fdaa13306 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1589430 Reviewed-by: Terje Bergstrom Reviewed-by: svc-mobile-coverity Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 39f9572c..faa67f02 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -30,7 +30,6 @@ #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" -#include "gk20a/ctxsw_trace_gk20a.h" #include "gk20a/fecs_trace_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/mc_gk20a.h" @@ -90,6 +89,7 @@ #include #include #include +#include #include #include -- cgit v1.2.2 From 5b368d3e46b946ed2a6b1b70ad2ac600740e582a Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 7 Nov 2017 10:47:20 -0800 Subject: gpu: nvgpu: gv1xx: Move fuse override DT handling Move fuse override DT handling to Linux code. All the chip specific fuse override functions did the same thing, so delete the HAL and call the same function to read the DT overrides on all chips. Also remove the fuse override functionality from dGPU. There are no DT entries for PCIe devices, so it would've failed anyway. JIRA NVGPU-259 Change-Id: Ic672e25090cdfc207d9771ab61b6cf53185113a4 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1593693 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index faa67f02..ced5006d 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -300,7 +300,6 @@ static const struct gpu_ops gv11b_ops = { .suspend_contexts = gr_gp10b_suspend_contexts, .resume_contexts = gr_gk20a_resume_contexts, .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, - .fuse_override = gp10b_gr_fuse_override, .init_sm_id_table = gr_gv100_init_sm_id_table, .load_smid_config = gr_gv11b_load_smid_config, .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, -- cgit v1.2.2 From c87e85af0cd812c6e1c138d4d1e48c23e3aa6bd3 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 7 Nov 2017 09:31:37 -0800 Subject: gpu: nvgpu: Return GPU classes in get_litter_value Return GPU classes in HAL get_litter_value() instead of assigning them to GPU characteristics at HAL initialization time. JIRA NVGPU-259 Change-Id: I92cbadf3bd07292a8715d30843972def879795f5 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1593691 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index ced5006d..681ddf3a 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -196,6 +196,24 @@ int gv11b_get_litter_value(struct gk20a *g, int value) case GPU_LIT_FBPA_SHARED_BASE: ret = 0; break; + case GPU_LIT_TWOD_CLASS: + ret = FERMI_TWOD_A; + break; + case GPU_LIT_THREED_CLASS: + ret = VOLTA_A; + break; + case GPU_LIT_COMPUTE_CLASS: + ret = VOLTA_COMPUTE_A; + break; + case GPU_LIT_GPFIFO_CLASS: + ret = VOLTA_CHANNEL_GPFIFO_A; + break; + case GPU_LIT_I2M_CLASS: + ret = KEPLER_INLINE_TO_MEMORY_B; + break; + case GPU_LIT_DMA_COPY_CLASS: + ret = VOLTA_DMA_COPY_A; + break; default: nvgpu_err(g, "Missing definition %d", value); @@ -674,7 +692,6 @@ static const struct gpu_ops gv11b_ops = { int gv11b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; - struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; u32 val; bool priv_security; @@ -760,12 +777,5 @@ int gv11b_init_hal(struct gk20a *g) g->name = "gv11b"; - c->twod_class = FERMI_TWOD_A; - c->threed_class = VOLTA_A; - c->compute_class = VOLTA_COMPUTE_A; - c->gpfifo_class = VOLTA_CHANNEL_GPFIFO_A; - c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; - c->dma_copy_class = VOLTA_DMA_COPY_A; - return 0; } -- cgit v1.2.2 From 98bd673a7371940f24d37ad3a6d7b426995e737e Mon Sep 17 00:00:00 2001 From: Sami Kiminki Date: Fri, 15 Sep 2017 18:58:58 +0300 Subject: gpu: nvgpu: Remove PTE kind code for GV100/GV11B Remove gv11b_init_uncompressed_kind_map(), gv11b_init_kind_attr(), and the related kind setup code. They are not needed anymore. While we're doing these changes, remove a redundant assignment of g->bootstrap_owner in hal_gv100.c. Bug 1902982 Change-Id: Ib40d8f55cfbfa34143a3765c2b4913926ca021fd Signed-off-by: Sami Kiminki Reviewed-on: https://git-master.nvidia.com/r/1560931 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 681ddf3a..5d8bbbdb 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -771,8 +771,6 @@ int gv11b_init_hal(struct gk20a *g) } __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); - gv11b_init_uncompressed_kind_map(); - gv11b_init_kind_attr(); g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; g->name = "gv11b"; -- cgit v1.2.2 From af5e4a1bf63037e7618adfa11a950244df5883f2 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 15 Nov 2017 15:10:51 +0530 Subject: gpu: nvgpu: deprecate TSG/CHANNEL_SET_PRIORITY IOCTLs TSG/CHANNEL_SET_PRIORITY IOCTLs are deprecated and user space should be using combination of timeslice and interleave levels to decide the priority Hence remove the IOCTLs and all corresponding APIs Jira NVGPU-393 Change-Id: Idce925631653784e39864223dc418a99a7e7ca3c Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1598582 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 5d8bbbdb..fc059caa 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -467,7 +467,6 @@ static const struct gpu_ops gv11b_ops = { .alloc_inst = gk20a_fifo_alloc_inst, .free_inst = gk20a_fifo_free_inst, .setup_ramfc = channel_gv11b_setup_ramfc, - .channel_set_priority = gk20a_fifo_set_priority, .channel_set_timeslice = gk20a_fifo_set_timeslice, .default_timeslice_us = gk20a_fifo_default_timeslice_us, .setup_userd = gk20a_fifo_setup_userd, -- cgit v1.2.2