From 8fe633449f92d35b60a60de647a4e8fc1b5c8936 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 9 Nov 2017 14:13:25 -0800 Subject: gpu: nvgpu: Add check_priv_security fuse ops -New fuse ops is added to set NVGPU_SEC_PRIVSECURITY and NVGPU_SEC_SECUREGPCCS bits in g->enabled_flags during hal initialization -For igpu non simulation platforms, fuses are read to decide if gpu should be allowed to boot or not. --Do not boot gpu if priv_sec_en is set but wpr_enabled is not set to 1 or vpr_auto_fetch_disable is not set to 0 --With priv_sec_en set, all falcons have to boot in LS mode and this needs wpr_enabled set to 1 AND vpr_auto_fetch_disable set to 0. In this case gmmu tries to pull wpr and vpr settings from tegra mc Bug 2018223 Change-Id: Iceaa1b0b3214e9a3d6cef5d77a82e034302f748b Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1595454 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/hal_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index fc059caa..8278d4e5 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -61,6 +61,7 @@ #include "gp10b/mm_gp10b.h" #include "gp10b/pmu_gp10b.h" #include "gp10b/gr_gp10b.h" +#include "gp10b/fuse_gp10b.h" #include "gp106/pmu_gp106.h" #include "gp106/acr_gp106.h" @@ -684,6 +685,9 @@ static const struct gpu_ops gv11b_ops = { .priv_ring = { .isr = gp10b_priv_ring_isr, }, + .fuse = { + .check_priv_security = gp10b_fuse_check_priv_security, + }, .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, .get_litter_value = gv11b_get_litter_value, }; @@ -691,8 +695,6 @@ static const struct gpu_ops gv11b_ops = { int gv11b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; - u32 val; - bool priv_security; gops->ltc = gv11b_ops.ltc; gops->ce2 = gv11b_ops.ce2; @@ -717,23 +719,18 @@ int gv11b_init_hal(struct gk20a *g) #endif gops->falcon = gv11b_ops.falcon; gops->priv_ring = gv11b_ops.priv_ring; + gops->fuse = gv11b_ops.fuse; /* Lone functions */ gops->chip_init_gpu_characteristics = gv11b_ops.chip_init_gpu_characteristics; gops->get_litter_value = gv11b_ops.get_litter_value; - val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); - if (val) { - priv_security = true; - pr_err("priv security is enabled\n"); - } else { - priv_security = false; - pr_err("priv security is disabled\n"); - } __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false); - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, priv_security); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, priv_security); + + /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ + if (gops->fuse.check_priv_security(g)) + return -EINVAL; /* Do not boot gpu */ /* priv security dependent ops */ if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { -- cgit v1.2.2