From 55a5c57bc1fd532cc6d041fdfb70d90286894b35 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 7 Apr 2016 16:57:18 -0700 Subject: gpu: nvgpu: gv11b: added initial source code Bug 1735757 Change-Id: Iea7488551a437afa0dfc005c87ad1b9ab9673b6c Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1122123 GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 drivers/gpu/nvgpu/gv11b/gr_gv11b.h (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h new file mode 100644 index 00000000..c8912f91 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -0,0 +1,30 @@ +/* + * GV11B GPU GR + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_GR_GV11B_H_ +#define _NVGPU_GR_GV11B_H_ + +struct gpu_ops; + +enum { + VOLTA_CHANNEL_GPFIFO_A = 0xC36F, + VOLTA_A = 0xC397, + VOLTA_COMPUTE_A = 0xC3C0, + VOLTA_DMA_COPY_A = 0xC3B5, +}; + +void gv11b_init_gr(struct gpu_ops *ops); + +#endif -- cgit v1.2.2 From 66f64c86a838bb9bfec049e3676debd8998e8b08 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Mon, 18 Apr 2016 09:36:13 -0700 Subject: gpu: nvgpu: gv11b: fix sparse warnings Fixed following sparse warnings: drivers/gpu/nvgpu/gv11b/gv11b.c:21:5: warning: symbol 'gv11b_init_gpu_characteristics' was not declared. Should it be static? drivers/gpu/nvgpu/gv11b/hal_gv11b.c:36:5: warning: symbol 'gv11b_init_hal' was not declared. Should it be static? drivers/gpu/nvgpu/gv11b/gr_gv11b.c:766:5: warning: symbol 'gr_gv11b_alloc_buffer' was not declared. Should it be static? Bug 200088648 Change-Id: I327f9d69bf1853727d74d2c125cfab54c2f0e5b0 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1128299 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ken Adams --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index c8912f91..11f5fb47 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -26,5 +26,8 @@ enum { }; void gv11b_init_gr(struct gpu_ops *ops); +int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, + struct mem_desc *mem); + #endif -- cgit v1.2.2 From 20d4f2052a25053c716201e708b4caddda1c9a16 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 4 Oct 2016 15:24:46 -0700 Subject: gpu: nvgpu: gv11b: program sw veid bundles Program hw state with relevant sw veid bundles. JIRA GV11B-11 Change-Id: I2c5e02016ed41db9c9b7f85cc0b401abaa003d37 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1231598 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 11f5fb47..5f13aa5c 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -25,6 +25,9 @@ enum { VOLTA_DMA_COPY_A = 0xC3B5, }; +/* use magic number 99 for subctx litter value */ +#define GPU_LIT_NUM_SUBCTX 99 + void gv11b_init_gr(struct gpu_ops *ops); int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, struct mem_desc *mem); -- cgit v1.2.2 From 37f317a3c4033b54ab4bf47286fb9ebd48edb021 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 15 Sep 2016 14:43:55 -0700 Subject: gpu: nvgpu: gv11b: zcull programming Bug 1735760 Change-Id: Id801efb613b5740389bde5dc2cfff47232d0a0f3 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1221582 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 5f13aa5c..df03cd8a 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -31,6 +31,7 @@ enum { void gv11b_init_gr(struct gpu_ops *ops); int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, struct mem_desc *mem); - - +/*zcull*/ +void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries, + u32 *zcull_map_tiles); #endif -- cgit v1.2.2 From 35d2db64e28df6d65fed381c793f0954eed5eb7b Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 17 Oct 2016 10:39:18 -0700 Subject: gpu: nvgpu: gv11b: update gr cb callbacks Update gr cb callbacks with gv11b default sizes. Also updated sw method ids for volta. JIRA GV11B-11 Change-Id: I77cccedb7a017f378e2194cef98ea4b0bf7acd6b Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1237786 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index df03cd8a..fe5445d9 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -28,6 +28,11 @@ enum { /* use magic number 99 for subctx litter value */ #define GPU_LIT_NUM_SUBCTX 99 +#define NVC397_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC397_SET_GO_IDLE_TIMEOUT 0x022c + void gv11b_init_gr(struct gpu_ops *ops); int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, struct mem_desc *mem); -- cgit v1.2.2 From a674eeee419a68e27bec63e46200036f5f33c8ff Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 13 Jan 2017 14:24:36 -0800 Subject: gpu: nvgpu: gv11b: Support Stencil ZBC Pre-GP10X All chips prior to GP10X do not support ZBC (Zero Bandwidth Clear) to stencil part of the packed kinds (packed kinds refer to Z24S8 and Z32_X24S8 kinds). Clears for these kinds typically happen in two phases, depth phase and stencil phase. The depth clears can be compressed or ZBC-ed, whereas the stencil part is always uncompressed. Stencil ZBC in GP10X For GP10X both the depth and the stencil data for these packed kinds can be ZBC cleared. A given tile will be a cross product of the following states for depth and stencil. Depth: Uncompressed, 1-2 plane compressed, 3-4 plane compressed, ZBC index 0, ZBC index 1 Stencil: Uncompressed, ZBC index 0, ZBC index 1, ZBC index 2 JIRA GV11B-9 Change-Id: I3381fd6305a4fada64211176b8ef98f27b04089f Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1235520 Reviewed-by: Terje Bergstrom Reviewed-by: Seshendra Gadagottu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index fe5445d9..d31c92ca 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -1,7 +1,7 @@ /* * GV11B GPU GR * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,6 +16,16 @@ #ifndef _NVGPU_GR_GV11B_H_ #define _NVGPU_GR_GV11B_H_ +#define GV11B_ZBC_TYPE_STENCIL T19X_ZBC +#define ZBC_STENCIL_CLEAR_FMT_INVAILD 0 +#define ZBC_STENCIL_CLEAR_FMT_U8 1 + +struct zbc_s_table { + u32 stencil; + u32 format; + u32 ref_cnt; +}; + struct gpu_ops; enum { -- cgit v1.2.2 From 64ab12979590564db19c820ff8cdd71579a9b317 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 11 Jan 2017 14:28:32 -0800 Subject: gpu: nvgpu: gv11b: sw methods for shader exception Added proper sw methods handling of shader execptions for gv11b. Bug 1834201 Change-Id: I3f3a45beed777cc4af59368dccd9dc7bb8181c37 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1283729 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index d31c92ca..b2549edd 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -43,6 +43,8 @@ enum { #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc #define NVC397_SET_GO_IDLE_TIMEOUT 0x022c +#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 + void gv11b_init_gr(struct gpu_ops *ops); int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, struct mem_desc *mem); -- cgit v1.2.2 From 207e2ac7d12e62df476f4828136a4c15e156f8a6 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 22 Feb 2017 10:04:31 -0800 Subject: gpu: nvgpu: gv11b: reading max veid number To get maximum number of subctx, sw should read NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT instead of LITTER_NUM_SUBCTX. JIRA GV11B-72 Change-Id: I4d675ba49d8a600da77e7b60da449d9e5ba48971 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1309591 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seema Khowala GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index b2549edd..7467fea8 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -35,9 +35,6 @@ enum { VOLTA_DMA_COPY_A = 0xC3B5, }; -/* use magic number 99 for subctx litter value */ -#define GPU_LIT_NUM_SUBCTX 99 - #define NVC397_SET_SHADER_EXCEPTIONS 0x1528 #define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280 #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc -- cgit v1.2.2 From c876bec8bab5a1e4d6dea529700ef19c5eac5e64 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Wed, 22 Mar 2017 10:01:14 -0700 Subject: gpu: nvgpu: rename mem_desc to nvgpu_mem $ find -type f | \ xargs sed -i 's/struct mem_desc/struct nvgpu_mem/g' JIRA NVGPU-12 Change-Id: I2b5d015e45185269bfae7c6d4199fe843ff26834 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1326194 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 7467fea8..9d9f969d 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -44,7 +44,7 @@ enum { void gv11b_init_gr(struct gpu_ops *ops); int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, - struct mem_desc *mem); + struct nvgpu_mem *mem); /*zcull*/ void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries, u32 *zcull_map_tiles); -- cgit v1.2.2 From ffc37e50fa8e869e9a160b35f3cf414040e8a360 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Wed, 10 May 2017 12:38:08 +0530 Subject: gpu: nvgpu: gv11b: Add L1 tags parity support This CL covers the following parity support (corrected + uncorrected), 1) SM's L1 tags 2) SM's S2R's pixel PRF buffer 3) SM's L1 D-cache miss latency FIFOs Volta Resiliency Id - Volta-720, Volta-721, Volta-637 JIRA GPUT19X-85 JIRA GPUT19X-104 JIRA GPUT19X-100 JIRA GPUT19X-103 Bug 1825948 Bug 1825962 Bug 1775457 Change-Id: I53d7231a36b2c7c252395eca27b349eca80dec63 Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1478881 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 9d9f969d..2d6e3d1f 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -35,6 +35,13 @@ enum { VOLTA_DMA_COPY_A = 0xC3B5, }; +struct gr_t19x { + struct { + struct gr_gp10b_ecc_stat sm_l1_tag_corrected_err_count; + struct gr_gp10b_ecc_stat sm_l1_tag_uncorrected_err_count; + } ecc_stats; +}; + #define NVC397_SET_SHADER_EXCEPTIONS 0x1528 #define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280 #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc @@ -48,4 +55,5 @@ int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, /*zcull*/ void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries, u32 *zcull_map_tiles); +void gr_gv11b_create_sysfs(struct device *dev); #endif -- cgit v1.2.2 From d503a234440b0b5912f64314de68689b3211bbcd Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Mon, 15 May 2017 15:32:21 +0530 Subject: gpu: nvgpu: gv11b: Add LRF + CBU parity support This CL covers the following parity support (uncorrected error), 1) SM's LRF 2) SM's CBU Volta Resiliency Id - Volta-637 JIRA GPUT19X-85 JIRA GPUT19X-110 Bug 1775457 Change-Id: I3befb1fe22719d06aa819ef27654aaf97f911a9b Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1481791 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 2d6e3d1f..b350862c 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -39,6 +39,8 @@ struct gr_t19x { struct { struct gr_gp10b_ecc_stat sm_l1_tag_corrected_err_count; struct gr_gp10b_ecc_stat sm_l1_tag_uncorrected_err_count; + struct gr_gp10b_ecc_stat sm_cbu_corrected_err_count; + struct gr_gp10b_ecc_stat sm_cbu_uncorrected_err_count; } ecc_stats; }; -- cgit v1.2.2 From 5a08eafbe076fba98de62883636ee6b0751cf7e9 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Wed, 17 May 2017 11:42:24 +0530 Subject: gpu: nvgpu: gv11b: Add L1 DATA + iCACHE parity This CL covers the following parity support (uncorrected error), 1) SM's L1 DATA 2) SM's L0 && L1 icache Volta Resiliency Id - Volta-634 JIRA GPUT19X-113 JIRA GPUT19X-99 Bug 1807553 Change-Id: Iacbf492028983529dadc5753007e43510b8cb786 Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1483681 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index b350862c..5bcbe667 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -41,6 +41,10 @@ struct gr_t19x { struct gr_gp10b_ecc_stat sm_l1_tag_uncorrected_err_count; struct gr_gp10b_ecc_stat sm_cbu_corrected_err_count; struct gr_gp10b_ecc_stat sm_cbu_uncorrected_err_count; + struct gr_gp10b_ecc_stat sm_l1_data_corrected_err_count; + struct gr_gp10b_ecc_stat sm_l1_data_uncorrected_err_count; + struct gr_gp10b_ecc_stat sm_icache_corrected_err_count; + struct gr_gp10b_ecc_stat sm_icache_uncorrected_err_count; } ecc_stats; }; -- cgit v1.2.2 From 45ca7cb8c5774cfc15015973b1883faa1d93b9e6 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Fri, 19 May 2017 15:40:41 +0530 Subject: gpu: nvgpu: gv11b: Add GCC L1.5 parity support Add handling of GCC L1.5 parity exception. JIRA GPUT19X-86 Change-Id: Ie83fc306d3dff79b0ddaf2616dcf0ff71fccd4ca Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1485834 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 5bcbe667..cf3842b6 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -45,6 +45,8 @@ struct gr_t19x { struct gr_gp10b_ecc_stat sm_l1_data_uncorrected_err_count; struct gr_gp10b_ecc_stat sm_icache_corrected_err_count; struct gr_gp10b_ecc_stat sm_icache_uncorrected_err_count; + struct gr_gp10b_ecc_stat gcc_l15_corrected_err_count; + struct gr_gp10b_ecc_stat gcc_l15_uncorrected_err_count; } ecc_stats; }; -- cgit v1.2.2 From c771d0b979cd9f42a21da520d5010873d2a6aa47 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 18 May 2017 16:45:40 -0700 Subject: gpu: nvgpu: add GPC parity counters (1) Re-arrange the structure for ecc counters reporting so multiple units can be managed (2) Add counters and handling for additional GPC counters JIRA: GPUT19X-84 Change-Id: I74fd474d7daf7590fc7f7ddc9837bb692512d208 Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1485277 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index cf3842b6..9283a597 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -35,21 +35,6 @@ enum { VOLTA_DMA_COPY_A = 0xC3B5, }; -struct gr_t19x { - struct { - struct gr_gp10b_ecc_stat sm_l1_tag_corrected_err_count; - struct gr_gp10b_ecc_stat sm_l1_tag_uncorrected_err_count; - struct gr_gp10b_ecc_stat sm_cbu_corrected_err_count; - struct gr_gp10b_ecc_stat sm_cbu_uncorrected_err_count; - struct gr_gp10b_ecc_stat sm_l1_data_corrected_err_count; - struct gr_gp10b_ecc_stat sm_l1_data_uncorrected_err_count; - struct gr_gp10b_ecc_stat sm_icache_corrected_err_count; - struct gr_gp10b_ecc_stat sm_icache_uncorrected_err_count; - struct gr_gp10b_ecc_stat gcc_l15_corrected_err_count; - struct gr_gp10b_ecc_stat gcc_l15_uncorrected_err_count; - } ecc_stats; -}; - #define NVC397_SET_SHADER_EXCEPTIONS 0x1528 #define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280 #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc -- cgit v1.2.2 From 5572bfa86a6afc7ae3c2f4a61e568f8e759c6ecc Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 22 Jun 2017 14:43:05 -0700 Subject: gpu: nvgpu: gv11b: sw method for NVC397_SET_TEX_IN_DBG Added sw method for NVC397_SET_TEX_IN_DBG with following data fields: data:0 PRI_TEX_IN_DBG_TSL1_RVCH_INVALIDATE data:1 PRI_SM_L1TAG_CTRL_CACHE_SURFACE_LD data:2 PRI_SM_L1TAG_CTRL_CACHE_SURFACE_ST Bug 1934197 Change-Id: I0956d3f5c859ac23e16fb6b7372acd098dfb6d16 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master/r/1507479 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Tested-by: Wei Sun Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 9283a597..ff5782d9 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -39,6 +39,11 @@ enum { #define NVC397_SET_CIRCULAR_BUFFER_SIZE 0x1280 #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc #define NVC397_SET_GO_IDLE_TIMEOUT 0x022c +#define NVC397_SET_TEX_IN_DBG 0x10bc + +#define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 0x1 +#define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD 0x2 +#define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST 0x4 #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 -- cgit v1.2.2 From df022d27ddf2f66bff04170bb454fa26db8d51b1 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Sat, 8 Jul 2017 17:20:26 -0700 Subject: gpu: nvgpu: gv11b: support SET_SKEDCHECK s/w methods Support sw method NVC397_SET_SKEDCHECK and NVC3C0_SET_SKEDCHECK data fields are data:0 SKEDCHECK_18_DISABLE data:1 SKEDCHECK_18_ENABLE Bug 200315442 Change-Id: I0652434ab0b4d6e49dab94be329072861e99c38c Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1515772 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index ff5782d9..1e060bd0 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -40,11 +40,19 @@ enum { #define NVC397_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc #define NVC397_SET_GO_IDLE_TIMEOUT 0x022c #define NVC397_SET_TEX_IN_DBG 0x10bc +#define NVC397_SET_SKEDCHECK 0x10c0 #define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 0x1 #define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD 0x2 #define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_ST 0x4 +#define NVC397_SET_SKEDCHECK_18_MASK 0x3 +#define NVC397_SET_SKEDCHECK_18_DEFAULT 0x0 +#define NVC397_SET_SKEDCHECK_18_DISABLE 0x1 +#define NVC397_SET_SKEDCHECK_18_ENABLE 0x2 + +#define NVC3C0_SET_SKEDCHECK 0x23c + #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 void gv11b_init_gr(struct gpu_ops *ops); -- cgit v1.2.2 From 2272cedfbacf271a0faacfd054240fea3027423d Mon Sep 17 00:00:00 2001 From: Lauri Peltonen Date: Mon, 10 Jul 2017 15:06:31 +0300 Subject: gpu: nvgu: Support SET_BES_CROP_DEBUG3 sw method The new SET_BES_CROP_DEBUG3 sw method is used to flip two fields in the NV_PGRAPH_PRI_BES_CROP_DEBUG3 register. The sw method is used by the user space driver to disable enough ROP optimizations to maintain ZBC state of target tiles. Bug 1942454 Change-Id: I3109fb4120674b15db4998693d0aa65bf0c3c8b5 Signed-off-by: Lauri Peltonen Reviewed-on: https://git-master.nvidia.com/r/1516205 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 1e060bd0..e6149b37 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -41,6 +41,7 @@ enum { #define NVC397_SET_GO_IDLE_TIMEOUT 0x022c #define NVC397_SET_TEX_IN_DBG 0x10bc #define NVC397_SET_SKEDCHECK 0x10c0 +#define NVC397_SET_BES_CROP_DEBUG3 0x10c4 #define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 0x1 #define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD 0x2 -- cgit v1.2.2 From 7ab28a41842df2045533b0836233db3563cd531f Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 6 Jun 2017 12:04:46 -0700 Subject: gpu: nvgpu: gv11b: support egpc and etpc context regoptype - implement is_egpc_addr, is_etpc_addr and get_egpc_etpc_num gr ops - implement decode and create priv addr for egpc/etpc JIRA GPUT19X-49 Bug 200311674 Signed-off-by: Seema Khowala Change-Id: Ia0cef51b2064df28460711185cd90b60aac03e4f Reviewed-on: https://git-master.nvidia.com/r/1522450 GVS: Gerrit_Virtual_Submit Reviewed-by: Tushar Kashalikar Tested-by: Tushar Kashalikar Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index e6149b37..0793dae5 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -16,6 +16,9 @@ #ifndef _NVGPU_GR_GV11B_H_ #define _NVGPU_GR_GV11B_H_ +#define EGPC_PRI_BASE 0x580000 +#define EGPC_PRI_SHARED_BASE 0x480000 + #define GV11B_ZBC_TYPE_STENCIL T19X_ZBC #define ZBC_STENCIL_CLEAR_FMT_INVAILD 0 #define ZBC_STENCIL_CLEAR_FMT_U8 1 -- cgit v1.2.2 From 2b98e1308d49b9c941d8fa6fc87f67108d6d9370 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Mon, 24 Jul 2017 12:19:53 -0700 Subject: gpu: nvgpu: gv11b: Remove privsecurity from gpu_ops Replace privsecurity boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_PRIVSECURITY Jira NVGPU-74 Change-Id: I4c11e3a89a76abe137cf61b69ad0fbcd665554b7 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1525714 Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 0793dae5..69148554 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -29,7 +29,7 @@ struct zbc_s_table { u32 ref_cnt; }; -struct gpu_ops; +struct gk20a; enum { VOLTA_CHANNEL_GPFIFO_A = 0xC36F, @@ -59,7 +59,7 @@ enum { #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 -void gv11b_init_gr(struct gpu_ops *ops); +void gv11b_init_gr(struct gk20a *g); int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, struct nvgpu_mem *mem); /*zcull*/ -- cgit v1.2.2 From 866165749a0b7b2e6b219bb26bffd69d790d97c5 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Thu, 17 Aug 2017 16:10:42 -0700 Subject: gpu: nvgpu: Reorg gr HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the gr sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I8feaa95a9830969221f7ac70a5ef61cdf25094c3 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1542988 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 140 ++++++++++++++++++++++++++++++++++++- 1 file changed, 139 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 69148554..9adace63 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -30,6 +30,9 @@ struct zbc_s_table { }; struct gk20a; +struct zbc_entry; +struct zbc_query_params; +struct channel_ctx_gk20a; enum { VOLTA_CHANNEL_GPFIFO_A = 0xC36F, @@ -59,11 +62,146 @@ enum { #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 -void gv11b_init_gr(struct gk20a *g); int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, struct nvgpu_mem *mem); /*zcull*/ void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries, u32 *zcull_map_tiles); void gr_gv11b_create_sysfs(struct device *dev); + +bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num); +bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num); +bool gr_gv11b_is_valid_compute_class(struct gk20a *g, u32 class_num); +void gr_gv11b_enable_hww_exceptions(struct gk20a *g); +void gr_gv11b_enable_exceptions(struct gk20a *g); +int gr_gv11b_handle_tpc_sm_ecc_exception(struct gk20a *g, + u32 gpc, u32 tpc, + bool *post_event, struct channel_gk20a *fault_ch, + u32 *hww_global_esr); +int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, + bool *post_event, struct channel_gk20a *fault_ch, + u32 *hww_global_esr); +int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc, + u32 gpc_exception); +int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, + u32 gpc_exception); +void gr_gv11b_enable_gpc_exceptions(struct gk20a *g); +int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, + bool *post_event); +int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_query_params *query_params); +bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_entry *zbc_val, int *ret_val); +int gr_gv11b_add_zbc_stencil(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_entry *stencil_val, u32 index); +int gr_gv11b_load_stencil_default_tbl(struct gk20a *g, + struct gr_gk20a *gr); +int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr); +u32 gr_gv11b_pagepool_default_size(struct gk20a *g); +int gr_gv11b_calc_global_ctx_buffer_size(struct gk20a *g); +int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, + u32 class_num, u32 offset, u32 data); +void gr_gv11b_bundle_cb_defaults(struct gk20a *g); +void gr_gv11b_cb_size_default(struct gk20a *g); +void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data); +void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data); +int gr_gv11b_dump_gr_status_regs(struct gk20a *g, + struct gk20a_debug_output *o); +int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms, + u32 expect_delay); +void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, + struct channel_ctx_gk20a *ch_ctx, + u64 addr, bool patch); +void gr_gv11b_init_cyclestats(struct gk20a *g); +void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); +void gr_gv11b_get_access_map(struct gk20a *g, + u32 **whitelist, int *num_entries); +int gr_gv11b_pre_process_sm_exception(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr, + bool sm_debugger_attached, struct channel_gk20a *fault_ch, + bool *early_exit, bool *ignore_debugger); +int gr_gv11b_handle_fecs_error(struct gk20a *g, + struct channel_gk20a *__ch, + struct gr_gk20a_isr_data *isr_data); +int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr); +int gr_gv11b_init_sw_veid_bundle(struct gk20a *g); +void gr_gv11b_detect_sm_arch(struct gk20a *g); +void gr_gv11b_init_sm_id_table(struct gk20a *g); +void gr_gv11b_program_sm_id_numbering(struct gk20a *g, + u32 gpc, u32 tpc, u32 smid); +int gr_gv11b_load_smid_config(struct gk20a *g); +int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va); +int gr_gv11b_commit_global_timeslice(struct gk20a *g, + struct channel_gk20a *c, bool patch); +void gv11b_restore_context_header(struct gk20a *g, + struct nvgpu_mem *ctxheader); +void gr_gv11b_write_zcull_ptr(struct gk20a *g, + struct nvgpu_mem *mem, u64 gpu_va); +void gr_gv11b_write_pm_ptr(struct gk20a *g, + struct nvgpu_mem *mem, u64 gpu_va); +void gr_gv11b_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine); +void gr_gv11b_load_tpc_mask(struct gk20a *g); +void gr_gv11b_set_preemption_buffer_va(struct gk20a *g, + struct nvgpu_mem *mem, u64 gpu_va); +int gr_gv11b_init_fs_state(struct gk20a *g); +void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, + u32 *esr_sm_sel); +int gv11b_gr_sm_trigger_suspend(struct gk20a *g); +void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state); +int gv11b_gr_update_sm_error_state(struct gk20a *g, + struct channel_gk20a *ch, u32 sm_id, + struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state); +int gv11b_gr_set_sm_debug_mode(struct gk20a *g, + struct channel_gk20a *ch, u64 sms, bool enable); +int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc); +void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g); +bool gv11b_gr_sm_debugger_attached(struct gk20a *g); +void gv11b_gr_suspend_single_sm(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm, + u32 global_esr_mask, bool check_errors); +void gv11b_gr_suspend_all_sms(struct gk20a *g, + u32 global_esr_mask, bool check_errors); +void gv11b_gr_resume_single_sm(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm); +void gv11b_gr_resume_all_sms(struct gk20a *g); +int gv11b_gr_resume_from_pause(struct gk20a *g); +u32 gv11b_gr_get_sm_hww_warp_esr(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm); +u32 gv11b_gr_get_sm_hww_global_esr(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm); +u32 gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g); +int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm, + u32 global_esr_mask, bool check_errors); +int gv11b_gr_lock_down_sm(struct gk20a *g, + u32 gpc, u32 tpc, u32 sm, u32 global_esr_mask, + bool check_errors); +void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, + u32 global_esr); +int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g, + u32 gpc, u32 tpc, bool *post_event); +void gv11b_gr_init_ovr_sm_dsm_perf(void); +void gv11b_gr_init_sm_dsm_reg_info(void); +void gv11b_gr_get_sm_dsm_perf_regs(struct gk20a *g, + u32 *num_sm_dsm_perf_regs, + u32 **sm_dsm_perf_regs, + u32 *perf_register_stride); +void gv11b_gr_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, + u32 *num_sm_dsm_perf_ctrl_regs, + u32 **sm_dsm_perf_ctrl_regs, + u32 *ctrl_register_stride); +void gv11b_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs, + u32 **ovr_perf_regs); +void gv11b_gr_access_smpc_reg(struct gk20a *g, u32 quad, u32 offset); +bool gv11b_gr_pri_is_egpc_addr(struct gk20a *g, u32 addr); +bool gv11b_gr_pri_is_etpc_addr(struct gk20a *g, u32 addr); +void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr, + u32 *egpc_num, u32 *etpc_num); +int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type, + u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags); +void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, + u32 gpc, u32 broadcast_flags, u32 *priv_addr_table, u32 *t); +u32 gv11b_gr_get_egpc_base(struct gk20a *g); +void gr_gv11b_init_gpc_mmu(struct gk20a *g); + #endif -- cgit v1.2.2 From d61643c0200983dc340d37962bb0a3ca900a3e97 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 25 Sep 2017 08:59:28 -0700 Subject: gpu: nvgpu: gv11b: Change license for common files to MIT Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity Reviewed-by: David Martinez Nieto Reviewed-by: Seshendra Gadagottu Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 9adace63..8880fbdd 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _NVGPU_GR_GV11B_H_ -- cgit v1.2.2 From 9825a8ec69d54c725c38015006aed655d10ac567 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 15 Aug 2017 15:28:35 -0700 Subject: gpu: nvgpu: fix handling of EGPC_ETPC_SM addresses Implemented litter values for following defines: GPU_LIT_SMPC_PRI_BASE GPU_LIT_SMPC_PRI_SHARED_BASE GPU_LIT_SMPC_PRI_UNIQUE_BASE9 GPU_LIT_SMPC_PRI_STRIDE Added broadcast flags for smpc Handled all combinations of broadcast/unicast EGPC, ETPC, SM Bug 200337994 Change-Id: I7aa3c4d9ac4e819010061d44fb5a40056762f518 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1539075 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 8880fbdd..3f06fe77 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -28,6 +28,8 @@ #define EGPC_PRI_BASE 0x580000 #define EGPC_PRI_SHARED_BASE 0x480000 +#define PRI_BROADCAST_FLAGS_SMPC BIT(17) + #define GV11B_ZBC_TYPE_STENCIL T19X_ZBC #define ZBC_STENCIL_CLEAR_FMT_INVAILD 0 #define ZBC_STENCIL_CLEAR_FMT_U8 1 -- cgit v1.2.2 From 99cae3dff71433c21f85bb7f03e42050db8a33dc Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 13 Oct 2017 08:12:58 -0700 Subject: gpu: nvgpu: gv11b: Use internal nvgpu_warpstate Replace use of ioctl structure warpstate with internal nvgpu_warptate. JIRA NVGPU-259 Change-Id: I003c15152042e566124c04d6124e515e36157c88 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1578683 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 3f06fe77..dbaee5a7 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -44,6 +44,7 @@ struct gk20a; struct zbc_entry; struct zbc_query_params; struct channel_ctx_gk20a; +struct nvgpu_warpstate; enum { VOLTA_CHANNEL_GPFIFO_A = 0xC36F, @@ -158,7 +159,7 @@ int gr_gv11b_init_fs_state(struct gk20a *g); void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, u32 *esr_sm_sel); int gv11b_gr_sm_trigger_suspend(struct gk20a *g); -void gv11b_gr_bpt_reg_info(struct gk20a *g, struct warpstate *w_state); +void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state); int gv11b_gr_update_sm_error_state(struct gk20a *g, struct channel_gk20a *ch, u32 sm_id, struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state); -- cgit v1.2.2 From 387ecf8a6360f463a129ab569aaef921fe0a2b0e Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 18 Oct 2017 11:40:46 -0700 Subject: gpu: nvgpu: gv1xx: Remove HAL for restore_context_header gr restore_context_header is not required any more after enabling per context va mode for subcontext. Cleaning-up unused function pointers from gv100 and gv11b HAL. Change-Id: I65cc7d12d3c96726d323defd99726c3e259e7e63 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1581432 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index dbaee5a7..ed469abd 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -145,8 +145,6 @@ int gr_gv11b_load_smid_config(struct gk20a *g); int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va); int gr_gv11b_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c, bool patch); -void gv11b_restore_context_header(struct gk20a *g, - struct nvgpu_mem *ctxheader); void gr_gv11b_write_zcull_ptr(struct gk20a *g, struct nvgpu_mem *mem, u64 gpu_va); void gr_gv11b_write_pm_ptr(struct gk20a *g, -- cgit v1.2.2 From c6ccb5f2a1e9a8999436f6c28ed5c416c5418ae3 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 23 Oct 2017 10:20:12 -0700 Subject: gpu: nvgpu: gv11b: use scg perf for smid numbering For SCG to work, smid numbering needs to be done based on scg performance of tpcs. For gv11b and gv11b vgpu, reuse gv100 function "gr_gv100_init_sm_id_table" to do this. Used local variable "index" to avoid multiple computations in the function: gr_gv100_init_sm_id_table index = sm_id + sm Add deug info for printing initialized gpc/tpc/sm/global_tpc indexs. Bug 1842197 Change-Id: Ibf10f47f10a8ca58b86c307a22e159b2cc0d0f43 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1583916 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index ed469abd..e469d142 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -138,7 +138,6 @@ int gr_gv11b_handle_fecs_error(struct gk20a *g, int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr); int gr_gv11b_init_sw_veid_bundle(struct gk20a *g); void gr_gv11b_detect_sm_arch(struct gk20a *g); -void gr_gv11b_init_sm_id_table(struct gk20a *g); void gr_gv11b_program_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid); int gr_gv11b_load_smid_config(struct gk20a *g); -- cgit v1.2.2 From 1cbb5ea0235f15180b1d4299499cab85db23c5ce Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Fri, 13 Oct 2017 17:15:46 -0700 Subject: gpu: nvgpu: init_cyclestats fixes - in the native case, replace calls for init_cyclestats with the gm20b version, as each chip had identical versions of the code. - in the virtual case, use the vgpu version of the function in order to get the new max_css_buffer_size characteristic set to the mempool size. JIRA ESRM-54 Bug 200296210 Change-Id: I475876cb392978fb1350ede58e37d0962ae095c3 Signed-off-by: Peter Daifuku Reviewed-on: https://git-master.nvidia.com/r/1578934 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index e469d142..71975e24 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -124,7 +124,6 @@ int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms, void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx, u64 addr, bool patch); -void gr_gv11b_init_cyclestats(struct gk20a *g); void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); void gr_gv11b_get_access_map(struct gk20a *g, u32 **whitelist, int *num_entries); -- cgit v1.2.2 From 33c707d60b116845c953b91c2693a82a4d1eb968 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 25 Oct 2017 14:33:05 -0700 Subject: gpu: nvgpu: Linux specific sm_error_state_record Create an nvgpu internal nvgpu_gr_sm_error_state to store and propagate SM error state within driver. Use nvgpu_dbg_gpu_sm_error_state_record only in Linux code. JIRA NVGPU-259 Change-Id: Ia2b347d0054365bdc790b4d6f2653a568935bdb0 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1585646 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 71975e24..feebef44 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -45,6 +45,7 @@ struct zbc_entry; struct zbc_query_params; struct channel_ctx_gk20a; struct nvgpu_warpstate; +struct nvgpu_gr_sm_error_state; enum { VOLTA_CHANNEL_GPFIFO_A = 0xC36F, @@ -158,7 +159,7 @@ int gv11b_gr_sm_trigger_suspend(struct gk20a *g); void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state); int gv11b_gr_update_sm_error_state(struct gk20a *g, struct channel_gk20a *ch, u32 sm_id, - struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state); + struct nvgpu_gr_sm_error_state *sm_error_state); int gv11b_gr_set_sm_debug_mode(struct gk20a *g, struct channel_gk20a *ch, u64 sms, bool enable); int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc); -- cgit v1.2.2 From e5c3b05bb2775236679b74194e4ac24612ef39b6 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 30 Oct 2017 19:28:43 +0530 Subject: gpu: nvgpu: use struct gk20a for create_gr_sysfs API gr_gv11b_create_sysfs() and GR HAL create_gr_sysfs() right now receive linux specific struct device But since this function is called from/declared in common code, we need to remove linux dependency from it Hence update the API and GR HAL to receive struct gk20a pointer instead of device pointer Jira NVGPU-259 Change-Id: I65d717ad9f263f0397f8efa5761c64e55c7846eb Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1588465 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index feebef44..98e7bc50 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -80,7 +80,7 @@ int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, /*zcull*/ void gr_gv11b_program_zcull_mapping(struct gk20a *g, u32 zcull_num_entries, u32 *zcull_map_tiles); -void gr_gv11b_create_sysfs(struct device *dev); +void gr_gv11b_create_sysfs(struct gk20a *g); bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num); bool gr_gv11b_is_valid_gfx_class(struct gk20a *g, u32 class_num); -- cgit v1.2.2 From 0f5202368781c5398e3d026dc408d79a37ad5aed Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Wed, 8 Nov 2017 18:32:26 -0800 Subject: gpu: nvgpu: ctx_patch_write fixes - Update commit_global_timeslice to remove unused patch parameter - Update calls to ctx_patch_write_begin/end to add update_patch_count param JIRA ESRM-74 Bug 2012077 Change-Id: Ie2e640dfa0ab7193a062a58f588575f220e5efd3 Signed-off-by: Peter Daifuku Reviewed-on: https://git-master.nvidia.com/r/1594791 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 98e7bc50..b6ba231e 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -142,8 +142,7 @@ void gr_gv11b_program_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid); int gr_gv11b_load_smid_config(struct gk20a *g); int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va); -int gr_gv11b_commit_global_timeslice(struct gk20a *g, - struct channel_gk20a *c, bool patch); +int gr_gv11b_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c); void gr_gv11b_write_zcull_ptr(struct gk20a *g, struct nvgpu_mem *mem, u64 gpu_va); void gr_gv11b_write_pm_ptr(struct gk20a *g, -- cgit v1.2.2