From 791ce6bd5480a8393c12be55e8afa459cb4dd1ff Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 23 Jan 2018 12:16:40 -0800 Subject: gpu: nvgpu: gv11b: enable more gr exceptions -pd, scc, ds, ssync, mme and sked exceptions are enabled. This will be useful for debugging -Handle enabled interrupts -Add gr ops to handle ssync hww. For legacy chips, ssync hww_esr register is gpcs_ppcs_ssync_hww_esr. Since ssync hww is not enabled on legacy chips, added ssync hww exception handling for volta only. Change-Id: I63ba2eb51fa82e74832df26ee4cf3546458e5669 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1644751 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 157c567a..2f8d2e17 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -227,5 +227,6 @@ int gr_gv11b_set_ctxsw_preemption_mode(struct gk20a *g, void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, struct channel_gk20a *ch_ctx, struct nvgpu_mem *mem); +int gr_gv11b_handle_ssync_hww(struct gk20a *g); #endif -- cgit v1.2.2