From 6a46965eb3b7b657c089142579ab20d6efefc0fc Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Wed, 6 Jun 2018 20:46:03 -0700 Subject: gpu: nvgpu: correct calculation of sm_id for .record_sm_error_state Starting with Volta, one TPC could have more than 1 SMs. So .record_sm_error_state needs to have sm number as parameter. Logic tpc id should be read from gr_gpc0_gpm_pd_sm_id_r. Let the function return logical sm_id. RM server will need it to nofify client. Jira EVLR-2643 Bug 200405202 Change-Id: Iffaff05b89b1c5058616b8a6bf50dd73bd4e52f6 Signed-off-by: Richard Zhao Reviewed-on: https://git-master.nvidia.com/r/1742165 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index b4a7e411..f6f05a3b 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -171,7 +171,7 @@ int gv11b_gr_update_sm_error_state(struct gk20a *g, struct nvgpu_gr_sm_error_state *sm_error_state); int gv11b_gr_set_sm_debug_mode(struct gk20a *g, struct channel_gk20a *ch, u64 sms, bool enable); -int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, +int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, struct channel_gk20a *fault_ch); void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g); bool gv11b_gr_sm_debugger_attached(struct gk20a *g); -- cgit v1.2.2