From cedb24c7a09292ec8deee9ee17e1d7defeff0241 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 18 Sep 2017 10:46:06 -0700 Subject: gpu: nvgpu: gv11b: correct wl reg offset Corrected whitelist register address offset for gr_pri_gpcs_tpcs_sm_disp_ctrl. This offset value is changed for gv11b from gp10b. With wrong offset value, gl tests are generating "unhandled fecs error interrupt 0x00000002 for channel xxx". Bug 1958308 Change-Id: Iabfbb20ea1ee4ca8567d0cda940fa1e8cbff1bac Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1562615 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 078272d1..ee49a8f2 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -1740,7 +1740,7 @@ void gr_gv11b_get_access_map(struct gk20a *g, 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */ 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */ 0x419e84, /* gr_pri_gpcs_tpcs_sms_dbgr_control0 */ - 0x419f78, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */ + 0x419ba4, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */ }; *whitelist = wl_addr_gv11b; -- cgit v1.2.2