From bacbc7331223b0f80b36d7eff43009e5d7ac9aae Mon Sep 17 00:00:00 2001 From: Alexander Lewkowicz Date: Fri, 4 Aug 2017 15:51:42 -0700 Subject: gpu: nvgpu: gv11b: Fix computation of offset When reading NV_PGRAPH_PRI_GPC0_TPC1_SM1_DBGR_STATUS0, we are not reading the expected value. The offset of the sm is not added to the PRI. JIRA GPUT19X-75 bug: ? Change-Id: I2eeb24505e928044c3a3331fa5f493a3f118a3c8 Signed-off-by: Alexander Lewkowicz Reviewed-on: https://git-master.nvidia.com/r/1533953 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index b95152eb..2b0e8be7 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -3116,7 +3116,7 @@ static int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g, u32 warp_esr, global_esr; struct nvgpu_timeout timeout; u32 offset = gk20a_gr_gpc_offset(g, gpc) + - gk20a_gr_tpc_offset(g, tpc); + gk20a_gr_tpc_offset(g, tpc) + gv11b_gr_sm_offset(g, sm); gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, -- cgit v1.2.2