From ae47fa042c2b7379079d54be13df001911954b9e Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 8 Jun 2018 16:25:49 -0700 Subject: gpu: nvgpu: populate vsm mapping based on nonpes_aware_tpc For gv1xx, kernel smid configuration programming is done based on nonpes aware tpc. For user space to be in sync with hw populate vsm mapping based on nonpes_aware_tpcs. Bug 200405202 Change-Id: Id89291ca64c2118915dc6f18f62e17f411d467b0 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1744304 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index f57be9dd..694ff8ad 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2661,7 +2661,7 @@ void gr_gv11b_detect_sm_arch(struct gk20a *g) gr_gpc0_tpc0_sm_arch_warp_count_v(v); } -static u32 gr_gv11b_get_nonpes_aware_tpc(struct gk20a *g, u32 gpc, u32 tpc) +u32 gr_gv11b_get_nonpes_aware_tpc(struct gk20a *g, u32 gpc, u32 tpc) { u32 tpc_new = 0; u32 temp; @@ -2691,7 +2691,7 @@ void gr_gv11b_program_sm_id_numbering(struct gk20a *g, u32 tpc_offset = tpc_in_gpc_stride * tpc; u32 global_tpc_index = g->gr.sm_to_cluster[smid].global_tpc_index; - tpc = gr_gv11b_get_nonpes_aware_tpc(g, gpc, tpc); + tpc = g->ops.gr.get_nonpes_aware_tpc(g, gpc, tpc); gk20a_writel(g, gr_gpc0_tpc0_sm_cfg_r() + gpc_offset + tpc_offset, gr_gpc0_tpc0_sm_cfg_tpc_id_f(global_tpc_index)); -- cgit v1.2.2