From 8e523a9a53088cd6b8645ab2b9ea8b3cd7cd5e9d Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 30 Jan 2018 13:05:47 -0800 Subject: gpu: nvgpu: gv11b: disable cbm alpha/beta cache invalidates Disabled CBM alpha and beta cache invalidates as required by hw. Since these registers are context switched out, added these invalidates as part of gr init sequence, so golden context restore these settings for all contexts. Bug 2040262 Change-Id: Iffdd03f2ac6440ddd615899c407cfee692460918 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1648948 Reviewed-by: Sami Kiminki Tested-by: Sami Kiminki Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Tested-by: Chris Dragan Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 61529a01..857f4944 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2711,6 +2711,14 @@ int gr_gv11b_init_fs_state(struct gk20a *g) gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()); gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data); + /* Disable CBM alpha and beta invalidations for l2 */ + data = gk20a_readl(g, gr_gpcs_ppcs_cbm_debug_r()); + data = set_field(data, gr_gpcs_ppcs_cbm_debug_invalidate_alpha_m(), + gr_gpcs_ppcs_cbm_debug_invalidate_alpha_disable_f()); + data = set_field(data, gr_gpcs_ppcs_cbm_debug_invalidate_beta_m(), + gr_gpcs_ppcs_cbm_debug_invalidate_beta_disable_f()); + gk20a_writel(g, gr_gpcs_ppcs_cbm_debug_r(), data); + data = gk20a_readl(g, gr_gpcs_tpcs_sm_disp_ctrl_r()); data = set_field(data, gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(), gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f()); -- cgit v1.2.2