From 650171566bff59e9eb372f213fdce4dfbb6da5bd Mon Sep 17 00:00:00 2001 From: Philemon Gardet Date: Fri, 20 Jul 2018 20:37:54 -0700 Subject: gpu: nvgpu: gv100: Fix nonpes aware tpc mapping For gv1xx, kernel smid configuration programming is done based on nonpes aware tpc. On gv100 the registers GPM_PD_SM_ID and SM_CFG are indexed on nonpes aware tpc. Bug 2096878 Change-Id: I0edc2f066e2c3b35057fde102689a9f1915c72ea Signed-off-by: Philemon Gardet Reviewed-on: https://git-master.nvidia.com/r/1783046 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Sandarbh Jain Tested-by: Sandarbh Jain Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 5d237839..ee736d15 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -2746,13 +2746,14 @@ void gr_gv11b_program_sm_id_numbering(struct gk20a *g, u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); u32 gpc_offset = gpc_stride * gpc; - u32 tpc_offset = tpc_in_gpc_stride * tpc; u32 global_tpc_index = g->gr.sm_to_cluster[smid].global_tpc_index; + u32 tpc_offset; tpc = g->ops.gr.get_nonpes_aware_tpc(g, gpc, tpc); + tpc_offset = tpc_in_gpc_stride * tpc; gk20a_writel(g, gr_gpc0_tpc0_sm_cfg_r() + gpc_offset + tpc_offset, - gr_gpc0_tpc0_sm_cfg_tpc_id_f(global_tpc_index)); + gr_gpc0_tpc0_sm_cfg_tpc_id_f(global_tpc_index)); gk20a_writel(g, gr_gpc0_gpm_pd_sm_id_r(tpc) + gpc_offset, gr_gpc0_gpm_pd_sm_id_id_f(global_tpc_index)); gk20a_writel(g, gr_gpc0_tpc0_pe_cfg_smid_r() + gpc_offset + tpc_offset, -- cgit v1.2.2