From 10c3d4447d4206302f5d51695bf1f193255dd889 Mon Sep 17 00:00:00 2001 From: Ashish Srivastava Date: Tue, 20 Feb 2018 17:10:27 +0530 Subject: gpu: nvgpu: gv11b: enable RMW for gpu atomics Separate HAL added in gv11b and gv100 for init_gpc_mmu function. In gv11b HAL, RMW is enabled for gpu atomics as default. In gv100 HAL, GPC atomic capability mode will get set based on the FB MMU capability. If GPU is connected through NVLINK then mmu will be set to RMW mode, else it will be in L2 mode. Bug 200390336 Change-Id: I224934f83d1762ec864ef8da7265dd01d86893a0 Signed-off-by: Ashish Srivastava Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1735137 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/gr_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index aed45ceb..1336557a 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -4263,7 +4263,13 @@ void gr_gv11b_init_gpc_mmu(struct gk20a *g) gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() | gr_gpcs_pri_mmu_ctrl_mmu_vol_m() | gr_gpcs_pri_mmu_ctrl_mmu_disable_m(); + + temp = set_field(temp, gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_m(), + gr_gpcs_pri_mmu_ctrl_atomic_capability_mode_rmw_f()); gk20a_writel(g, gr_gpcs_pri_mmu_ctrl_r(), temp); + nvgpu_log_info(g, "mmu_ctrl_r = 0x%08x, atomic_capability_mode_rmw", + temp); + gk20a_writel(g, gr_gpcs_pri_mmu_pm_unit_mask_r(), 0); gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0); -- cgit v1.2.2