From c84ddceda648d6e47828115654ca7745010ec09f Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 14 Apr 2016 13:01:58 -0700 Subject: gpu: nvgpu: gv11b: sm priv reg related changes Included all basic ops for gv11b and updated sm related functions to include new priv register addresses. Bug 1735757 Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1126961 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 drivers/gpu/nvgpu/gv11b/fifo_gv11b.h (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h new file mode 100644 index 00000000..5b95ad9e --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -0,0 +1,20 @@ +/* + * GV11B Fifo + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef FIFO_GV11B_H +#define FIFO_GV11B_H +struct gpu_ops; +void gv11b_init_fifo(struct gpu_ops *gops); +#endif -- cgit v1.2.2 From 2766420dfbe15e539a4b9514bbf41480fc636a28 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 16 Mar 2017 15:04:29 -0700 Subject: gpu: nvgpu: gv11b: implement teardown_ch_tsg fifo ops Context TSG teardown procedure: 1. Disable scheduling for the engine's runlist via NV_PFIFO_SCHED_DISABLE. This enables SW to determine whether a context has hung later in the process: otherwise, ongoing work on the runlist may keep ENG_STATUS from reaching a steady state. 2. Disable all channels in the TSG being torn down or submit a new runlist that does not contain the TSG. This is to prevent the TSG from being rescheduled once scheduling is reenabled in step 6. 3. Initiate a preempt of the engine by writing the bit associated with its runlist to NV_PFIFO_RUNLIST_PREEMPT. This allows to begin the preempt process prior to doing the slow register reads needed to determine whether the context has hit any interrupts or is hung. Do not poll NV_PFIFO_RUNLIST_PREEMPT for the preempt to complete. 4. Check for interrupts or hangs while waiting for the preempt to complete. During the pbdma/eng preempt finish polling, any stalling interrupts relating to runlist must be detected and handled in order for the preemption to complete. 5. If a reset is needed as determined by step 4: a. Halt the memory interface for the engine (as per the relevant engine procedure). b. Reset the engine via NV_PMC_ENABLE. c. Take the engine out of reset and reinit the engine (as per relevant engine procedure) 6. Re-enable scheduling for the engine's runlist via NV_PFIFO_SCHED_ENABLE. JIRA GPUT19X-7 Change-Id: I1354dd12b4a4f0e4b4a8d9721581126c02288a85 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1327931 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 5b95ad9e..07a39da0 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -15,6 +15,9 @@ #ifndef FIFO_GV11B_H #define FIFO_GV11B_H + +#define FIFO_INVAL_PBDMA_ID ((u32)~0) + struct gpu_ops; void gv11b_init_fifo(struct gpu_ops *gops); #endif -- cgit v1.2.2 From 457f176785af5c8821889d00d89db05bbaf8f772 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 8 Mar 2017 22:34:49 -0800 Subject: gpu: nvgpu: gv11b: init handle sched_error & ctxsw_timout ops - detect and decode sched_error type. Any sched error starting with xxx_* is not supported in h/w and should never be seen by s/w - for bad_tsg sched error, preempt all runlists to recover as faulted ch/tsg is unknown. For other errors, just report error. - ctxsw timeout is not part of sched error fifo interrupt. A new fifo interrupt, ctxsw timeout is added in gv11b. Add s/w handling. Bug 1856152 JIRA GPUT19X-74 Change-Id: I474e1a3cda29a450691fe2ea1dc1e239ce57df1a Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1317615 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 07a39da0..ab56b876 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -18,6 +18,20 @@ #define FIFO_INVAL_PBDMA_ID ((u32)~0) +/* engine context-switch request occurred while the engine was in reset */ +#define SCHED_ERROR_CODE_ENGINE_RESET 0x00000005 + +/* +* ERROR_CODE_BAD_TSG indicates that Host encountered a badly formed TSG header +* or a badly formed channel type runlist entry in the runlist. This is typically +* caused by encountering a new TSG entry in the middle of a TSG definition. +* A channel type entry having wrong runqueue selector can also cause this. +* Additionally this error code can indicate when a channel is encountered on +* the runlist which is outside of a TSG. +*/ +#define SCHED_ERROR_CODE_BAD_TSG 0x00000020 + + struct gpu_ops; void gv11b_init_fifo(struct gpu_ops *gops); #endif -- cgit v1.2.2 From 8a0221cfc735f79c94447ff5922e26c313e0f177 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 27 Jun 2017 16:36:48 -0700 Subject: gpu: nvgpu: gv11b: implement eng method buffer init/deinit When CE hits a page fault it needs to save out methods, it will save it out to a per runqueue per TSG method buffer. The method buffers (one per TSG runqueue) are allocated in BAR2 space during TSG creation All channels in a TSG that are mapped to the same runqueue will point to the same buffer. S/w will insert channel's method buffer pointer in the channel's instance block entries NV_RAMIN_ENG_METHOD_BUFFER_ADDR_LO and NV_RAMIN_ENG_METHOD_BUFFER_ADDR_HI. Method buffer in memory will be 32B aligned. Eng method buffer allocated per tsg will be de-allocated during tsg_release. JIRA GPUT19X-46 Change-Id: Ib480ae5840d9815d24fe2eadc169ac3102854cd0 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1509747 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index ab56b876..94b7934f 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -31,6 +31,10 @@ */ #define SCHED_ERROR_CODE_BAD_TSG 0x00000020 +/* can be removed after runque support is added */ + +#define GR_RUNQUE 0 /* pbdma 0 */ +#define ASYNC_CE_RUNQUE 2 /* pbdma 2 */ struct gpu_ops; void gv11b_init_fifo(struct gpu_ops *gops); -- cgit v1.2.2 From 5cda5a3074e4c7dae1857e1dfdf55017b0450786 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 27 Jun 2017 22:10:49 -0700 Subject: gpu: nvgpu: gv11b: add a function to reset pbdma and eng faulted When Host receives a page fault signal from a CE, Host will immediately set _ENG_FAULTED bit in the NV_PCCSR_CHANNEL register for the channel and will trigger a preempt of the TSG/channel. A channel will only be scheduled when _ENABLED=1, _ENG_FAULTED=0 and _PBDMA_FAULTED=0 in pccsr_channel reg for the channel. If a TSG has a faulted channel, Host will not schedule the entire TSG agin until all _FAULTED bits from channels in the TSG are cleared by SW. This function will be required for ce page fault handling. JIRA GPUT19X-46 JIRA GPUT19X-12 Change-Id: Ib58dff7aa24aa144e970f11b5261877dec03f3e6 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1509776 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 94b7934f..03cca839 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -38,4 +38,7 @@ struct gpu_ops; void gv11b_init_fifo(struct gpu_ops *gops); +void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g, + struct channel_gk20a *refch, + u32 faulted_pbdma, u32 faulted_engine); #endif -- cgit v1.2.2 From 6d758eb81bcbff4e50df5c9fa67a369a4e1f2074 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 29 Jun 2017 15:59:05 -0700 Subject: gpu: nvgpu: gv11b: support for full subcontext Changes to enable 64 subcontexts: 1 SYNC + 63 ASYNC Currently all subcontexts with in a tsg can have only single address space. Add support for NVGPU_TSG_IOCTL_BIND_CHANNEL_EX for selecting subctx id by client. Bug 1842197 Change-Id: Icf56a41303bd1ad7fc6f2a6fbc691bb7b4a01d22 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master/r/1511145 Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 03cca839..032342b2 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -1,7 +1,7 @@ /* * GV11B Fifo * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -36,6 +36,8 @@ #define GR_RUNQUE 0 /* pbdma 0 */ #define ASYNC_CE_RUNQUE 2 /* pbdma 2 */ +#define CHANNEL_INFO_VEID0 0 + struct gpu_ops; void gv11b_init_fifo(struct gpu_ops *gops); void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g, -- cgit v1.2.2 From 2f6d321390a98ace1e52f21c6a399e06b3fe71e7 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 7 Mar 2017 12:16:07 -0800 Subject: gpu: nvgpu: gv11b: add mmu fault handling HUB reports following memory sub-system interrupts: a) ACCESS_COUNTER_NOTIFY: GET != PUT for access counter notify buffer b) ACCESS_COUNTER_ERROR: HUB received a NACK (BAR2 fault) when writing the notify buffer out to memory c) MMU_ECC_UNCORRECTED_ERROR_NOTIFY: Uncorrected ECC error detected by HUB MMU d) MMU_REPLAYABLE_FAULT_NOTIFY: GET != PUT for replayable fault buffer e) MMU_REPLAYABLE_FAULT_OVERFLOW: Overflow when writing to the replayable fault buffer f) MMU_NONREPLAYABLE_FAULT_NOTIFY: GET != PUT for non-replayable fault buffer g) MMU_NONREPLAYABLE_FAULT_OVERFLOW: Overflow when writing to the non-replayable fault buffer h) MMU_OTHER_FAULT_NOTIFY: All other fault notifications from MMU This change is to : -Detect other fault notify -Copy fault info from fault snap register for other fault notify interrupt -Detect and handle nonreplay/replay fault notify and fault overflow -Copy fault info from fault buffer for nonreplay/replay fault -Print fault info JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: Ifa08a4ebcd119a7d81c2eae3f52dc825d1ce3898 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1493394 Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 032342b2..8a2b32f8 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -17,6 +17,7 @@ #define FIFO_GV11B_H #define FIFO_INVAL_PBDMA_ID ((u32)~0) +#define FIFO_INVAL_VEID ((u32)~0) /* engine context-switch request occurred while the engine was in reset */ #define SCHED_ERROR_CODE_ENGINE_RESET 0x00000005 @@ -43,4 +44,6 @@ void gv11b_init_fifo(struct gpu_ops *gops); void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g, struct channel_gk20a *refch, u32 faulted_pbdma, u32 faulted_engine); +void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g, + u32 mmu_fault_id, u32 *active_engine_id, u32 *veid, u32 *pbdma_id); #endif -- cgit v1.2.2 From 8140c51e6cd212517fc343e6f8f8694bbad98f3b Mon Sep 17 00:00:00 2001 From: Sunny He Date: Fri, 30 Jun 2017 15:54:03 -0700 Subject: gpu: nvgpu: gv11b: Reorg fifo HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fifo sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I7c81edfa785a4ecafef41aae7b82d6b1707d294e Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1522554 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 58 +++++++++++++++++++++++++++++++++++- 1 file changed, 57 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 8a2b32f8..3fb2f6e9 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -40,10 +40,66 @@ #define CHANNEL_INFO_VEID0 0 struct gpu_ops; -void gv11b_init_fifo(struct gpu_ops *gops); + void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g, struct channel_gk20a *refch, u32 faulted_pbdma, u32 faulted_engine); void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g, u32 mmu_fault_id, u32 *active_engine_id, u32 *veid, u32 *pbdma_id); + +void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist); +void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist); +int channel_gv11b_setup_ramfc(struct channel_gk20a *c, + u64 gpfifo_base, u32 gpfifo_entries, + unsigned long acquire_timeout, u32 flags); +u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c); +u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c); +void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c); +void channel_gv11b_unbind(struct channel_gk20a *ch); +u32 gv11b_fifo_get_num_fifos(struct gk20a *g); +bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid); +void gv11b_dump_channel_status_ramfc(struct gk20a *g, + struct gk20a_debug_output *o, + u32 chid, + struct ch_state *ch_state); +void gv11b_dump_eng_status(struct gk20a *g, + struct gk20a_debug_output *o); +u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g); +int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, + unsigned int id_type, unsigned int timeout_rc_type); +int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid); +int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid); +int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, + unsigned int id_type, unsigned int timeout_rc_type); +void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, + u32 id, unsigned int id_type, unsigned int rc_type, + struct mmu_fault_info *mmfault); +void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f); +int gv11b_init_fifo_reset_enable_hw(struct gk20a *g); +bool gv11b_fifo_handle_sched_error(struct gk20a *g); +bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr); +unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g, + u32 pbdma_id, u32 pbdma_intr_0, + u32 *handled, u32 *error_notifier); +unsigned int gv11b_fifo_handle_pbdma_intr_1(struct gk20a *g, + u32 pbdma_id, u32 pbdma_intr_1, + u32 *handled, u32 *error_notifier); +void gv11b_fifo_init_eng_method_buffers(struct gk20a *g, + struct tsg_gk20a *tsg); +void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g, + struct tsg_gk20a *tsg); +int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, + u32 syncpt_id, struct nvgpu_mem *syncpt_buf); +void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c, + struct nvgpu_mem *syncpt_buf); +void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, + struct priv_cmd_entry *cmd, u32 off, + u32 id, u32 thresh, u64 gpu_va_base); +u32 gv11b_fifo_get_syncpt_wait_cmd_size(void); +void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, + bool wfi_cmd, struct priv_cmd_entry *cmd, + u32 id, u64 gpu_va_base); +u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd); +int gv11b_init_fifo_setup_hw(struct gk20a *g); + #endif -- cgit v1.2.2 From 52f50addc6cedf57fc3d8ff06314921499fb59e3 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 13 Sep 2017 17:35:03 +0530 Subject: gpu: nvgpu: add TSG enable/disable operations Add TSG enable/disable operations for gv11b/gv100 To disable a TSG we continue to use gk20a_disable_tsg() To enable a TSG add new API gv11b_fifo_enable_tsg() since TSG enable sequence is different for Volta than previous versions For Volta it is sufficient to loop over all the channels in TSG and enable them sequentially Bug 1739362 Change-Id: Id4b4684959204c6101ceda83487a41fbfcba8b5f Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1560642 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 3fb2f6e9..e576714c 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -69,6 +69,7 @@ int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, unsigned int id_type, unsigned int timeout_rc_type); int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid); int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid); +int gv11b_fifo_enable_tsg(struct tsg_gk20a *tsg); int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, unsigned int id_type, unsigned int timeout_rc_type); void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, -- cgit v1.2.2 From f720b309f1ea87a301bcb216983396f3d9c55abc Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 14 Sep 2017 05:48:07 -0700 Subject: gpu: nvgpu: add tsg_verify_status_faulted operation Add new API gv11b_fifo_tsg_verify_status_faulted() and use that as g->ops.fifo.tsg_verify_status_faulted operation for gv11b/gv100 This API will check if channel has ENG_FAULTED status set, if yes it will clear CE method buffer in case saved out channel is same as faulted channel We need to write 0 to method count to invalidate CE method buffer Also set g->ops.fifo.tsg_verify_status_ctx_reload operation for gv11b/gv100 Bug 200327095 Change-Id: I9d2b0f13faf881b30680219bbcadfd4969c4dff6 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1560643 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index e576714c..0cc1c7c2 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -103,4 +103,6 @@ void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd); int gv11b_init_fifo_setup_hw(struct gk20a *g); +void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch); + #endif -- cgit v1.2.2 From d61643c0200983dc340d37962bb0a3ca900a3e97 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 25 Sep 2017 08:59:28 -0700 Subject: gpu: nvgpu: gv11b: Change license for common files to MIT Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity Reviewed-by: David Martinez Nieto Reviewed-by: Seshendra Gadagottu Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 0cc1c7c2..f622aba8 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -3,14 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef FIFO_GV11B_H -- cgit v1.2.2 From 6114553413297dbcae637bc50ef2ff2a6c0858d1 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 19 Oct 2017 10:12:24 -0700 Subject: gpu: nvgpu: gv100: fix timeout handling GV100 has a larger vidmem size and a slower sideband to sysmem so timeouts need to be adjusted to avoid false positives. JIRA: NVGPUGV100-36 Change-Id: I3cbc19aa1158c89bc48ae1fa6ec4bc755cd9389d Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1582092 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.h') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index f622aba8..fc1ddf83 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h @@ -113,5 +113,5 @@ u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd); int gv11b_init_fifo_setup_hw(struct gk20a *g); void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch); - +u32 gv11b_fifo_get_preempt_timeout(struct gk20a *g); #endif -- cgit v1.2.2