From e3ae03e17abd452c157545234348692364b4b9f6 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 12 Sep 2018 14:51:40 -0700 Subject: gpu: nvgpu: Add MC APIs for reset masks Add API for querying reset mask corresponding to a unit. The reset masks need to be read from MC HW header, and we do not want all units to access Mc HW headers themselves. JIRA NVGPU-954 Change-Id: I49ebbd891569de634bfc71afcecc8cd2358805c0 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1823384 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index fa1836c8..34e9cd5f 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -41,6 +41,7 @@ #include #include #include +#include #include "gk20a/fifo_gk20a.h" @@ -53,7 +54,6 @@ #include #include #include -#include #include #include "fifo_gv11b.h" @@ -1281,7 +1281,7 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) nvgpu_log_fn(g, " "); /* enable pmc pfifo */ - g->ops.mc.reset(g, mc_enable_pfifo_enabled_f()); + g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_FIFO)); if (g->ops.clock_gating.slcg_ce2_load_gating_prod) { g->ops.clock_gating.slcg_ce2_load_gating_prod(g, -- cgit v1.2.2