From c84ddceda648d6e47828115654ca7745010ec09f Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 14 Apr 2016 13:01:58 -0700 Subject: gpu: nvgpu: gv11b: sm priv reg related changes Included all basic ops for gv11b and updated sm related functions to include new priv register addresses. Bug 1735757 Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1126961 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 drivers/gpu/nvgpu/gv11b/fifo_gv11b.c (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c new file mode 100644 index 00000000..af5f094d --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -0,0 +1,28 @@ +/* + * GV11B fifo + * + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#include "gk20a/gk20a.h" +#include "gp10b/fifo_gp10b.h" +#include "hw_pbdma_gv11b.h" +#include "fifo_gv11b.h" +#include "hw_fifo_gv11b.h" + +void gv11b_init_fifo(struct gpu_ops *gops) +{ + gp10b_init_fifo(gops); +} -- cgit v1.2.2 From 8fdf40a849f19dc2f00aacce976ed2e22dbb08f4 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 13 Sep 2016 13:08:01 -0700 Subject: gpu: gv11b: create modified runlist Create gv11b runlist for channel and tsg in the new specified way. Also set runlist entry size for gv11b. Bug 1735760 Change-Id: Ifd421cd71180e9d02303f4cfc92a59fd74d6d893 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1220258 GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru Reviewed-by: Seema Khowala Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 63 ++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index af5f094d..35b36ec5 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -21,8 +21,71 @@ #include "hw_pbdma_gv11b.h" #include "fifo_gv11b.h" #include "hw_fifo_gv11b.h" +#include "hw_ram_gv11b.h" +#include "hw_ccsr_gv11b.h" + +static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) +{ + + u32 runlist_entry_0 = ram_rl_entry_type_tsg_v(); + + if (tsg->timeslice_timeout) + runlist_entry_0 |= + ram_rl_entry_tsg_timeslice_scale_f(tsg->timeslice_scale) | + ram_rl_entry_tsg_timeslice_timeout_f(tsg->timeslice_timeout); + else + runlist_entry_0 |= + ram_rl_entry_tsg_timeslice_scale_f( + ram_rl_entry_tsg_timeslice_scale_3_v()) | + ram_rl_entry_tsg_timeslice_timeout_f( + ram_rl_entry_tsg_timeslice_timeout_128_v()); + + runlist[0] = runlist_entry_0; + runlist[1] = ram_rl_entry_tsg_length_f(tsg->num_active_channels); + runlist[2] = ram_rl_entry_tsg_tsgid_f(tsg->tsgid); + runlist[3] = 0; + + gk20a_dbg_info("gv11b tsg runlist [0] %x [1] %x [2] %x [3] %x\n", + runlist[0], runlist[1], runlist[2], runlist[3]); + +} + +static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) +{ + struct gk20a *g = c->g; + u32 addr_lo, addr_hi; + u32 runlist_entry; + + /* Time being use 0 pbdma sequencer */ + runlist_entry = ram_rl_entry_type_channel_v() | + ram_rl_entry_chan_runqueue_selector_f(0) | + ram_rl_entry_chan_userd_target_f( + ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()) | + ram_rl_entry_chan_inst_target_f( + ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()); + + addr_lo = u64_lo32(c->userd_iova) >> + ram_rl_entry_chan_userd_ptr_align_shift_v(); + addr_hi = u64_hi32(c->userd_iova); + runlist[0] = runlist_entry | ram_rl_entry_chan_userd_ptr_lo_f(addr_lo); + runlist[1] = ram_rl_entry_chan_userd_ptr_hi_f(addr_hi); + + addr_lo = u64_lo32(gk20a_mm_inst_block_addr(g, &c->inst_block)) >> + ram_rl_entry_chan_inst_ptr_align_shift_v(); + addr_hi = u64_hi32(gk20a_mm_inst_block_addr(g, &c->inst_block)); + + runlist[2] = ram_rl_entry_chan_inst_ptr_lo_f(addr_lo) | + ram_rl_entry_chid_f(c->hw_chid); + runlist[3] = ram_rl_entry_chan_inst_ptr_hi_f(addr_hi); + + gk20a_dbg_info("gv11b channel runlist [0] %x [1] %x [2] %x [3] %x\n", + runlist[0], runlist[1], runlist[2], runlist[3]); +} void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); + gops->fifo.runlist_entry_size = ram_rl_entry_size_v; + gops->fifo.get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry; + gops->fifo.get_ch_runlist_entry = gv11b_get_ch_runlist_entry; } -- cgit v1.2.2 From 1a36091fb9e31578c2e01c60cbe0a9b01b64bc9e Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Sat, 24 Sep 2016 11:20:37 -0700 Subject: gpu: nvgpu: gv11b: sysmem userd support For gv11b, userd is allocated from sysmem. Updated gp_get and gp_put functions to read or write from sysmem instead of bar1 memory. In gv11b, after updating gp_put, it is required to notify pending work to host through channel doorbell. JIRA GV11B-1 Change-Id: Iebc52e6ccfc8b9ca0c57b227190e0ce1161076f1 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1226613 GVS: Gerrit_Virtual_Submit Reviewed-by: Konsta Holtta Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 47 ++++++++++++++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 35b36ec5..c6e0f0a2 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -12,17 +12,17 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. */ - #include #include - #include "gk20a/gk20a.h" +#include "gk20a/fifo_gk20a.h" #include "gp10b/fifo_gp10b.h" #include "hw_pbdma_gv11b.h" #include "fifo_gv11b.h" #include "hw_fifo_gv11b.h" #include "hw_ram_gv11b.h" #include "hw_ccsr_gv11b.h" +#include "hw_usermode_gv11b.h" static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) { @@ -82,10 +82,53 @@ static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) runlist[0], runlist[1], runlist[2], runlist[3]); } +static void gv11b_ring_channel_doorbell(struct channel_gk20a *c) +{ + gk20a_dbg_info("channel ring door bell %d\n", c->hw_chid); + + gk20a_writel(c->g, usermode_notify_channel_pending_r(), + usermode_notify_channel_pending_id_f(c->hw_chid)); +} + +static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) +{ + struct mem_desc *userd_mem = &g->fifo.userd; + u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); + + return gk20a_mem_rd32(g, userd_mem, + offset + ram_userd_gp_get_w()); + +} + +static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) +{ + struct mem_desc *userd_mem = &g->fifo.userd; + u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); + + gk20a_mem_wr32(g, userd_mem, offset + ram_userd_gp_put_w(), + c->gpfifo.put); + /* commit everything to cpu */ + smp_mb(); + + gv11b_ring_channel_doorbell(c); + +} + + +static u32 gv11b_fifo_get_num_fifos(struct gk20a *g) +{ + return ccsr_channel__size_1_v(); +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); + /* for gv11b no need to do any thing special for fifo hw setup */ + gops->fifo.init_fifo_setup_hw = NULL; gops->fifo.runlist_entry_size = ram_rl_entry_size_v; gops->fifo.get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry; gops->fifo.get_ch_runlist_entry = gv11b_get_ch_runlist_entry; + gops->fifo.get_num_fifos = gv11b_fifo_get_num_fifos; + gops->fifo.userd_gp_get = gv11b_userd_gp_get; + gops->fifo.userd_gp_put = gv11b_userd_gp_put; } -- cgit v1.2.2 From 2fd1ee0ca784e4235766601d6a7ef52ba1f0c519 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 17 Oct 2016 10:26:25 -0700 Subject: gpu: nvgpu: gv11b: update ramfc Updated ramfc: - To include channel veid info - Set valid context bit - Enabled userd writeback JIRA GV11B-11 Change-Id: I0e8c62fe0dee02071b0ca60f157151038ab5c09b Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1237764 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 86 ++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index c6e0f0a2..0e1c1999 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -24,6 +24,9 @@ #include "hw_ccsr_gv11b.h" #include "hw_usermode_gv11b.h" +#define CHANNEL_INFO_VEID0 0 +#define PBDMA_SUBDEVICE_ID 1 + static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) { @@ -82,6 +85,88 @@ static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) runlist[0], runlist[1], runlist[2], runlist[3]); } +static void gv11b_userd_writeback_config(struct gk20a *g) +{ + gk20a_writel(g, fifo_userd_writeback_r(), fifo_userd_writeback_timer_f( + fifo_userd_writeback_timer_100us_v())); + + +} + +static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, + u64 gpfifo_base, u32 gpfifo_entries, u32 flags) +{ + struct gk20a *g = c->g; + struct mem_desc *mem = &c->inst_block; + u32 data; + + gk20a_dbg_fn(""); + + gk20a_memset(g, mem, 0, 0, ram_fc_size_val_v()); + + gk20a_mem_wr32(g, mem, ram_fc_gp_base_w(), + pbdma_gp_base_offset_f( + u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s()))); + + gk20a_mem_wr32(g, mem, ram_fc_gp_base_hi_w(), + pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) | + pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries))); + + gk20a_mem_wr32(g, mem, ram_fc_signature_w(), + c->g->ops.fifo.get_pbdma_signature(c->g)); + + gk20a_mem_wr32(g, mem, ram_fc_pb_header_w(), + pbdma_pb_header_priv_user_f() | + pbdma_pb_header_method_zero_f() | + pbdma_pb_header_subchannel_zero_f() | + pbdma_pb_header_level_main_f() | + pbdma_pb_header_first_true_f() | + pbdma_pb_header_type_inc_f()); + + gk20a_mem_wr32(g, mem, ram_fc_subdevice_w(), + pbdma_subdevice_id_f(PBDMA_SUBDEVICE_ID) | + pbdma_subdevice_status_active_f() | + pbdma_subdevice_channel_dma_enable_f()); + + gk20a_mem_wr32(g, mem, ram_fc_target_w(), + pbdma_target_eng_ctx_valid_true_f() | + pbdma_target_engine_sw_f()); + + gk20a_mem_wr32(g, mem, ram_fc_acquire_w(), + channel_gk20a_pbdma_acquire_val(c)); + + gk20a_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(), + pbdma_runlist_timeslice_timeout_128_f() | + pbdma_runlist_timeslice_timescale_3_f() | + pbdma_runlist_timeslice_enable_true_f()); + + + gk20a_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); + + /* Until full subcontext is supported, always use VEID0 */ + gk20a_mem_wr32(g, mem, ram_fc_set_channel_info_w(), + pbdma_set_channel_info_scg_type_graphics_compute0_f() | + pbdma_set_channel_info_veid_f(CHANNEL_INFO_VEID0)); + + if (c->is_privileged_channel) { + /* Set privilege level for channel */ + gk20a_mem_wr32(g, mem, ram_fc_config_w(), + pbdma_config_auth_level_privileged_f()); + + gk20a_channel_setup_ramfc_for_privileged_channel(c); + } + + /* Enable userd writeback */ + data = gk20a_mem_rd32(g, mem, ram_fc_config_w()); + data = data | pbdma_config_userd_writeback_enable_f(); + gk20a_mem_wr32(g, mem, ram_fc_config_w(),data); + + gv11b_userd_writeback_config(g); + + return channel_gp10b_commit_userd(c); +} + + static void gv11b_ring_channel_doorbell(struct channel_gk20a *c) { gk20a_dbg_info("channel ring door bell %d\n", c->hw_chid); @@ -131,4 +216,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.get_num_fifos = gv11b_fifo_get_num_fifos; gops->fifo.userd_gp_get = gv11b_userd_gp_get; gops->fifo.userd_gp_put = gv11b_userd_gp_put; + gops->fifo.setup_ramfc = channel_gv11b_setup_ramfc; } -- cgit v1.2.2 From 4bac40b5b3a89054f53b2a608841d84d4262a8a7 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 16 Nov 2016 11:44:40 -0800 Subject: gpu: nvgpu: gv11b: set ce context valid Set copy engine context valid for channel loaded on pbdma. JIRA GV11B-21 Change-Id: I74445dcefe38b52723705c185e6a37c9f56ac2bf Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1254916 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 0e1c1999..bc413a9e 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -130,6 +130,7 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, gk20a_mem_wr32(g, mem, ram_fc_target_w(), pbdma_target_eng_ctx_valid_true_f() | + pbdma_target_ce_ctx_valid_true_f() | pbdma_target_engine_sw_f()); gk20a_mem_wr32(g, mem, ram_fc_acquire_w(), -- cgit v1.2.2 From 67b54c3c76cfa488e1d102e5c74a32b3aaba9287 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 16 Nov 2016 12:25:08 -0800 Subject: gpu: nvgpu: legacy support with subcontext gv11b needs atleast one subcontext to submit work. To support legacy in gv11b, currently main context is always copied into subcontext0 (veid0) during channel commit instance. As part of channel commit instance, veid0 for that channel is created and relevant pdb and context info copied to vedi0. JIRA GV11B-21 Change-Id: I5147a1708b5e94202fa55e73fa0e53199ab7fced Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1231169 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index bc413a9e..b9276e09 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -19,6 +19,8 @@ #include "gp10b/fifo_gp10b.h" #include "hw_pbdma_gv11b.h" #include "fifo_gv11b.h" +#include "subctx_gv11b.h" +#include "gr_gv11b.h" #include "hw_fifo_gv11b.h" #include "hw_ram_gv11b.h" #include "hw_ccsr_gv11b.h" @@ -200,6 +202,15 @@ static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) } +static void channel_gv11b_unbind(struct channel_gk20a *ch) +{ + gk20a_dbg_fn(""); + + gv11b_free_subctx_header(ch); + + channel_gk20a_unbind(ch); + +} static u32 gv11b_fifo_get_num_fifos(struct gk20a *g) { @@ -218,4 +229,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.userd_gp_get = gv11b_userd_gp_get; gops->fifo.userd_gp_put = gv11b_userd_gp_put; gops->fifo.setup_ramfc = channel_gv11b_setup_ramfc; + gops->fifo.unbind_channel = channel_gv11b_unbind; } -- cgit v1.2.2 From 4ad2d3aebc4137d350efaff8072d60441572bcf2 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 13 Jan 2017 13:32:09 -0800 Subject: gpu: nvgpu: gv11b: support for multiple runlists Add support for multiple runlists in gv11b. Bug 1834201 Change-Id: I5a4cb92643626675314b4b61df330cde06e22c9f Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1285044 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b9276e09..4929f4d1 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1,7 +1,7 @@ /* * GV11B fifo * - * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -230,4 +230,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.userd_gp_put = gv11b_userd_gp_put; gops->fifo.setup_ramfc = channel_gv11b_setup_ramfc; gops->fifo.unbind_channel = channel_gv11b_unbind; + gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; } -- cgit v1.2.2 From 4f3871309d5216b50179feed8f8024193b2224cf Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 13 Jan 2017 13:34:24 -0800 Subject: gpu: nvgpu: gv11b: restore golden context Restore golden context correctly with subcontext header. Increase subctx header size to hold complete golden context. Also fill function pointer for freeing context header. Bug 1834201 Change-Id: Id8a3437bc437fef02ee15333c1163290217d34d1 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1282440 Reviewed-by: Alex Waterman Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 4929f4d1..7f2f5a65 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -185,7 +185,6 @@ static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) return gk20a_mem_rd32(g, userd_mem, offset + ram_userd_gp_get_w()); - } static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) @@ -199,17 +198,13 @@ static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) smp_mb(); gv11b_ring_channel_doorbell(c); - } static void channel_gv11b_unbind(struct channel_gk20a *ch) { gk20a_dbg_fn(""); - gv11b_free_subctx_header(ch); - channel_gk20a_unbind(ch); - } static u32 gv11b_fifo_get_num_fifos(struct gk20a *g) @@ -231,4 +226,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.setup_ramfc = channel_gv11b_setup_ramfc; gops->fifo.unbind_channel = channel_gv11b_unbind; gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; + gops->fifo.free_channel_ctx_header = gv11b_free_subctx_header; } -- cgit v1.2.2 From 4b09997772f406d16945016ff4581c7c992faeab Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 12 Jan 2017 13:01:36 -0800 Subject: nvgpu: gpu: HW header update for Volta Similar HW header update as has been done for all the other chips. HW header files are located under: drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/ And can be included like so: #include Bug 1799159 Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1284433 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 7f2f5a65..ab32016e 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -14,17 +14,21 @@ */ #include #include + #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" + #include "gp10b/fifo_gp10b.h" -#include "hw_pbdma_gv11b.h" + +#include +#include +#include +#include +#include + #include "fifo_gv11b.h" #include "subctx_gv11b.h" #include "gr_gv11b.h" -#include "hw_fifo_gv11b.h" -#include "hw_ram_gv11b.h" -#include "hw_ccsr_gv11b.h" -#include "hw_usermode_gv11b.h" #define CHANNEL_INFO_VEID0 0 #define PBDMA_SUBDEVICE_ID 1 -- cgit v1.2.2 From 8497f45a2ed8599053ad0be99143c8effb510acf Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 7 Feb 2017 15:58:01 -0800 Subject: nvgpu: gpu: gv11b: Remove syncpt protection support In gv11b sync point support is moved to a shim outside of GPU, and gv11b does not support sync points anymore. Remove use of the sync point protection. JIRA GV11B-47 JIRA GV11B-2 Change-Id: I70f3d2ce0cfe016453efe03f2bbf64c59baeb154 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1300964 Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index ab32016e..cd6007ba 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -228,6 +228,7 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.userd_gp_get = gv11b_userd_gp_get; gops->fifo.userd_gp_put = gv11b_userd_gp_put; gops->fifo.setup_ramfc = channel_gv11b_setup_ramfc; + gops->fifo.resetup_ramfc = NULL; gops->fifo.unbind_channel = channel_gv11b_unbind; gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; gops->fifo.free_channel_ctx_header = gv11b_free_subctx_header; -- cgit v1.2.2 From a4ea94f5d12f9c983cbcb9624fa946c0806768f1 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 1 Mar 2017 10:42:31 -0800 Subject: gpu: nvgpu: init fifo ops for device_info_fault_id generated hw header for top_device_info_data_fault_id_enum_v is different between legacy chips and t19x JIRA GV11B-7 Change-Id: Ia765be740c419c5b2a61b03104b264c51f1e797e Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1313383 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index cd6007ba..5304f39f 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "fifo_gv11b.h" #include "subctx_gv11b.h" @@ -232,4 +233,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.unbind_channel = channel_gv11b_unbind; gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; gops->fifo.free_channel_ctx_header = gv11b_free_subctx_header; + gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v; } -- cgit v1.2.2 From 8d6a05fc5704ae5ce0c46c4ec2a8ce0c17aacf68 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 1 Mar 2017 12:01:37 -0800 Subject: gpu: nvgpu: gv11b: init is_fault_engine_subid_gpc ops *client_type_gpc_v moved from fifo to gmmu JIRA GV11B-7 Change-Id: Icd28a2ac8c0d0ae212cfca9410dfe781972367df Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1313435 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 5304f39f..7f19d3c8 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "fifo_gv11b.h" #include "subctx_gv11b.h" @@ -217,6 +218,11 @@ static u32 gv11b_fifo_get_num_fifos(struct gk20a *g) return ccsr_channel__size_1_v(); } +static bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid) +{ + return (engine_subid == gmmu_fault_client_type_gpc_v()); +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); @@ -234,4 +240,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; gops->fifo.free_channel_ctx_header = gv11b_free_subctx_header; gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v; + gops->fifo.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc; } -- cgit v1.2.2 From 5e4ca8f5e8fca20b8357056242356bc608e54e27 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 1 Mar 2017 15:51:32 -0800 Subject: gpu: nvgpu: gv11b: trigger mmu fault is not supported For gv11b fifo recovery, triggering fake mmu fault is not required. JIRA GV11B-7 Change-Id: I6c8c9672085dbbbd77e0d991d840c4cc75c2ab43 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1313496 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 7f19d3c8..656c5421 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -241,4 +241,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.free_channel_ctx_header = gv11b_free_subctx_header; gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v; gops->fifo.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc; + gops->fifo.trigger_mmu_fault = NULL; } -- cgit v1.2.2 From 679086c42ea58ce3c355e1dd8c17f662f84a2faf Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 9 Feb 2017 13:58:02 -0800 Subject: gpu: nvgpu: gv11b: support debug dump Added dump for pbdma, engine status, channel status and ramfc JIRA GV11B-45 Change-Id: I25442932c61310005fea481455f68ba10c361381 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1302425 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 93 +++++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 656c5421..e33b8ee2 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -15,8 +15,9 @@ #include #include +#include "nvgpu/semaphore.h" + #include "gk20a/gk20a.h" -#include "gk20a/fifo_gk20a.h" #include "gp10b/fifo_gp10b.h" @@ -223,6 +224,93 @@ static bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid) return (engine_subid == gmmu_fault_client_type_gpc_v()); } +static void gv11b_dump_channel_status_ramfc(struct gk20a *g, + struct gk20a_debug_output *o, + u32 hw_chid, + struct ch_state *ch_state) +{ + u32 channel = gk20a_readl(g, ccsr_channel_r(hw_chid)); + u32 status = ccsr_channel_status_v(channel); + u32 *inst_mem; + struct channel_gk20a *c = g->fifo.channel + hw_chid; + struct nvgpu_semaphore_int *hw_sema = NULL; + + if (c->hw_sema) + hw_sema = c->hw_sema; + + if (!ch_state) + return; + + inst_mem = &ch_state->inst_block[0]; + + gk20a_debug_output(o, "%d-%s, pid %d, refs: %d: ", hw_chid, + dev_name(g->dev), + ch_state->pid, + ch_state->refs); + gk20a_debug_output(o, "channel status: %s in use %s %s\n", + ccsr_channel_enable_v(channel) ? "" : "not", + gk20a_decode_ccsr_chan_status(status), + ccsr_channel_busy_v(channel) ? "busy" : "not busy"); + gk20a_debug_output(o, "RAMFC : TOP: %016llx PUT: %016llx GET: %016llx " + "FETCH: %016llx\nHEADER: %08x COUNT: %08x\n" + "SEMAPHORE: addr hi: %08x addr lo: %08x\n" + "payload %08x execute %08x\n", + (u64)inst_mem[ram_fc_pb_top_level_get_w()] + + ((u64)inst_mem[ram_fc_pb_top_level_get_hi_w()] << 32ULL), + (u64)inst_mem[ram_fc_pb_put_w()] + + ((u64)inst_mem[ram_fc_pb_put_hi_w()] << 32ULL), + (u64)inst_mem[ram_fc_pb_get_w()] + + ((u64)inst_mem[ram_fc_pb_get_hi_w()] << 32ULL), + (u64)inst_mem[ram_fc_pb_fetch_w()] + + ((u64)inst_mem[ram_fc_pb_fetch_hi_w()] << 32ULL), + inst_mem[ram_fc_pb_header_w()], + inst_mem[ram_fc_pb_count_w()], + inst_mem[ram_fc_sem_addr_hi_w()], + inst_mem[ram_fc_sem_addr_lo_w()], + inst_mem[ram_fc_sem_payload_lo_w()], + inst_mem[ram_fc_sem_execute_w()]); + if (hw_sema) + gk20a_debug_output(o, "SEMA STATE: value: 0x%08x " + "next_val: 0x%08x addr: 0x%010llx\n", + readl(hw_sema->value), + atomic_read(&hw_sema->next_value), + nvgpu_hw_sema_addr(hw_sema)); + gk20a_debug_output(o, "\n"); +} + +static void gv11b_dump_eng_status(struct gk20a *g, + struct gk20a_debug_output *o) +{ + u32 i, host_num_engines; + + host_num_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES); + + for (i = 0; i < host_num_engines; i++) { + u32 status = gk20a_readl(g, fifo_engine_status_r(i)); + u32 ctx_status = fifo_engine_status_ctx_status_v(status); + + gk20a_debug_output(o, "%s eng %d: ", dev_name(g->dev), i); + gk20a_debug_output(o, + "id: %d (%s), next_id: %d (%s), ctx status: %s ", + fifo_engine_status_id_v(status), + fifo_engine_status_id_type_v(status) ? + "tsg" : "channel", + fifo_engine_status_next_id_v(status), + fifo_engine_status_next_id_type_v(status) ? + "tsg" : "channel", + gk20a_decode_pbdma_chan_eng_ctx_status(ctx_status)); + + if (fifo_engine_status_eng_reload_v(status)) + gk20a_debug_output(o, "ctx_reload "); + if (fifo_engine_status_faulted_v(status)) + gk20a_debug_output(o, "faulted "); + if (fifo_engine_status_engine_v(status)) + gk20a_debug_output(o, "busy "); + gk20a_debug_output(o, "\n"); + } + gk20a_debug_output(o, "\n"); +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); @@ -242,4 +330,7 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v; gops->fifo.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc; gops->fifo.trigger_mmu_fault = NULL; + gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status; + gops->fifo.dump_eng_status = gv11b_dump_eng_status; + gops->fifo.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc; } -- cgit v1.2.2 From 18a0a89f4535d2f14e4a282ac01482a4c3e2e805 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 1 Mar 2017 15:27:13 -0800 Subject: gpu: nvgpu: init intr_0_error_mask fifo ops mmu fault is now part of hub interrupt Change-Id: I9ce523d5f11955ac9552510d154eaa2f17a6cbf6 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1313484 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index e33b8ee2..eb8f44d7 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -311,6 +311,18 @@ static void gv11b_dump_eng_status(struct gk20a *g, gk20a_debug_output(o, "\n"); } +static u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g) +{ + u32 intr_0_error_mask = + fifo_intr_0_bind_error_pending_f() | + fifo_intr_0_sched_error_pending_f() | + fifo_intr_0_chsw_error_pending_f() | + fifo_intr_0_fb_flush_timeout_pending_f() | + fifo_intr_0_lb_error_pending_f(); + + return intr_0_error_mask; +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); @@ -333,4 +345,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status; gops->fifo.dump_eng_status = gv11b_dump_eng_status; gops->fifo.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc; + gops->fifo.intr_0_error_mask = gv11b_fifo_intr_0_error_mask; } -- cgit v1.2.2 From 8929fb2b1db9ddb986070efd998772e56e669e70 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 22 Feb 2017 16:01:20 -0800 Subject: gpu: nvgpu: gv11b: implement is_preempt_pending preempt completion should be decided based on pbdma and engine status. preempt_pending field is no longer used to detect if preempt finished. add a new function to to be used for preeempting ch and tsg during recovery. If preempt timeouts while in recovery, do not issue recovery. JIRA GPUT19X-7 Change-Id: I0d69d12ee6a118f6628b33be5ba387c72983b32a Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1309850 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 305 +++++++++++++++++++++++++++++++++++ 1 file changed, 305 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index eb8f44d7..b671628a 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -16,6 +16,7 @@ #include #include "nvgpu/semaphore.h" +#include #include "gk20a/gk20a.h" @@ -323,6 +324,306 @@ static u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g) return intr_0_error_mask; } +static int gv11b_fifo_poll_pbdma_chan_status(struct gk20a *g, u32 id, + u32 pbdma_id, unsigned int timeout_rc_type) +{ + struct nvgpu_timeout timeout; + unsigned long delay = GR_IDLE_CHECK_DEFAULT; + u32 pbdma_stat; + u32 chan_stat; + int ret = -EBUSY; + + /* + * If the PBDMA has a stalling interrupt and receives a NACK, the PBDMA + * won't save out until the STALLING interrupt is cleared. Note that + * the stalling interrupt need not be directly addressed, as simply + * clearing of the interrupt bit will be sufficient to allow the PBDMA + * to save out. If the stalling interrupt was due to a SW method or + * another deterministic failure, the PBDMA will assert it when the + * channel is reloaded/resumed. Note that the fault will still be + * reported to SW. + */ + + if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { + /* called from recovery */ + u32 pbdma_intr_0, pbdma_intr_1; + + pbdma_intr_0 = gk20a_readl(g, pbdma_intr_0_r(pbdma_id)); + pbdma_intr_1 = gk20a_readl(g, pbdma_intr_1_r(pbdma_id)); + + if (pbdma_intr_0) + gk20a_writel(g, pbdma_intr_0_r(pbdma_id), pbdma_intr_0); + if (pbdma_intr_1) + gk20a_writel(g, pbdma_intr_1_r(pbdma_id), pbdma_intr_1); + } + + /* Verify that ch/tsg is no longer on the pbdma */ + do { + pbdma_stat = gk20a_readl(g, fifo_pbdma_status_r(pbdma_id)); + chan_stat = fifo_pbdma_status_chan_status_v(pbdma_stat); + + gk20a_dbg_info("wait preempt pbdma"); + + if (chan_stat == + fifo_pbdma_status_chan_status_valid_v() || + chan_stat == + fifo_pbdma_status_chan_status_chsw_save_v()) { + + if (id != fifo_pbdma_status_id_v(pbdma_stat)) { + ret = 0; + break; + } + + } else if (chan_stat == + fifo_pbdma_status_chan_status_chsw_load_v()) { + + if (id != fifo_pbdma_status_next_id_v(pbdma_stat)) { + ret = 0; + break; + } + + } else if (chan_stat == + fifo_pbdma_status_chan_status_chsw_switch_v()) { + + if ((id != fifo_pbdma_status_next_id_v(pbdma_stat)) && + (id != fifo_pbdma_status_id_v(pbdma_stat))) { + ret = 0; + break; + } + } else { + /* pbdma status is invalid i.e. it is not loaded */ + ret = 0; + break; + } + + usleep_range(delay, delay * 2); + delay = min_t(unsigned long, + delay << 1, GR_IDLE_CHECK_MAX); + } while (!nvgpu_timeout_expired_msg(&timeout, + "preempt timeout pbdma")); + return ret; +} + +static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, + u32 engine_idx, u32 *reset_eng_bitmask, + unsigned int timeout_rc_type) +{ + struct nvgpu_timeout timeout; + unsigned long delay = GR_IDLE_CHECK_DEFAULT; + u32 eng_stat; + u32 ctx_stat; + int ret = -EBUSY; + + /* Check if ch/tsg has saved off the engine or if ctxsw is hung */ + do { + eng_stat = gk20a_readl(g, fifo_engine_status_r(engine_idx)); + ctx_stat = fifo_engine_status_ctx_status_v(eng_stat); + + if (ctx_stat == + fifo_engine_status_ctx_status_ctxsw_switch_v()) { + gk20a_dbg_info("engine save hasn't started yet"); + + } else if (ctx_stat == + fifo_engine_status_ctx_status_valid_v() || + ctx_stat == + fifo_engine_status_ctx_status_ctxsw_save_v()) { + + if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { + /* called from recovery, eng seems to be hung */ + if (id == fifo_engine_status_id_v(eng_stat)) { + *reset_eng_bitmask |= BIT(engine_idx); + ret = 0; + break; + } + } + + } else if (ctx_stat == + fifo_engine_status_ctx_status_ctxsw_load_v()) { + + if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { + /* called from recovery, eng seems to be hung */ + if (id == + fifo_engine_status_next_id_v(eng_stat)) { + + *reset_eng_bitmask |= BIT(engine_idx); + ret = 0; + break; + } + } + + } else { + /* Preempt should be finished */ + ret = 0; + break; + } + + usleep_range(delay, delay * 2); + delay = min_t(unsigned long, + delay << 1, GR_IDLE_CHECK_MAX); + } while (!nvgpu_timeout_expired_msg(&timeout, + "preempt timeout engine")); + return ret; +} + +int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, + unsigned int id_type, unsigned int timeout_rc_type) +{ + struct fifo_gk20a *f = &g->fifo; + unsigned long runlist_served_pbdmas; + unsigned long runlist_served_engines; + u32 pbdma_id; + u32 act_eng_id; + u32 runlist_id; + int func_ret; + int ret = 0; + + gk20a_dbg_fn(""); + + if (id_type == ID_TYPE_TSG) + runlist_id = f->tsg[id].runlist_id; + else + runlist_id = f->channel[id].runlist_id; + + runlist_served_pbdmas = f->runlist_info[runlist_id].pbdma_bitmask; + runlist_served_engines = f->runlist_info[runlist_id].eng_bitmask; + + for_each_set_bit(pbdma_id, &runlist_served_pbdmas, f->num_pbdma) { + + func_ret = gv11b_fifo_poll_pbdma_chan_status(g, id, pbdma_id, + timeout_rc_type); + if (func_ret != 0) { + gk20a_dbg_info("preempt timeout pbdma %d", pbdma_id); + ret |= func_ret; + } + } + + f->runlist_info[runlist_id].reset_eng_bitmask = 0; + + for_each_set_bit(act_eng_id, &runlist_served_engines, f->num_engines) { + + func_ret = gv11b_fifo_poll_eng_ctx_status(g, id, act_eng_id, + &f->runlist_info[runlist_id].reset_eng_bitmask, + timeout_rc_type); + + if (func_ret != 0) { + gk20a_dbg_info("preempt timeout engine %d", act_eng_id); + ret |= func_ret; + } + } + + return ret; +} + +static int gv11b_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) +{ + struct fifo_gk20a *f = &g->fifo; + u32 ret = 0; + u32 token = PMU_INVALID_MUTEX_OWNER_ID; + u32 mutex_ret = 0; + u32 runlist_id; + + gk20a_dbg_fn("%d", hw_chid); + + runlist_id = f->channel[hw_chid].runlist_id; + gk20a_dbg_fn("runlist_id %d", runlist_id); + + nvgpu_mutex_acquire(&f->runlist_info[runlist_id].mutex); + + mutex_ret = pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + + ret = __locked_fifo_preempt(g, hw_chid, false); + + if (!mutex_ret) + pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + + nvgpu_mutex_release(&f->runlist_info[runlist_id].mutex); + + return ret; +} + +static int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) +{ + struct fifo_gk20a *f = &g->fifo; + u32 ret = 0; + u32 token = PMU_INVALID_MUTEX_OWNER_ID; + u32 mutex_ret = 0; + u32 runlist_id; + + gk20a_dbg_fn("%d", tsgid); + + runlist_id = f->tsg[tsgid].runlist_id; + gk20a_dbg_fn("runlist_id %d", runlist_id); + + nvgpu_mutex_acquire(&f->runlist_info[runlist_id].mutex); + + mutex_ret = pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + + ret = __locked_fifo_preempt(g, tsgid, true); + + if (!mutex_ret) + pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + + nvgpu_mutex_release(&f->runlist_info[runlist_id].mutex); + + return ret; +} + +static int __locked_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, + unsigned int id_type, unsigned int timeout_rc_type) +{ + int ret; + + /* issue preempt */ + gk20a_fifo_issue_preempt(g, id, id_type); + + /* wait for preempt */ + ret = g->ops.fifo.is_preempt_pending(g, id, id_type, + timeout_rc_type); + + if (ret && (timeout_rc_type == PREEMPT_TIMEOUT_RC)) + __locked_fifo_preempt_timeout_rc(g, id, id_type); + + return ret; +} + + +static int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, + unsigned int id_type, unsigned int timeout_rc_type) +{ + struct fifo_gk20a *f = &g->fifo; + u32 ret = 0; + u32 token = PMU_INVALID_MUTEX_OWNER_ID; + u32 mutex_ret = 0; + u32 runlist_id; + + if (id_type == ID_TYPE_TSG) + runlist_id = f->tsg[id].runlist_id; + else if (id_type == ID_TYPE_CHANNEL) + runlist_id = f->channel[id].runlist_id; + else + return -EINVAL; + + if (runlist_id >= g->fifo.max_runlists) { + gk20a_dbg_info("runlist_id = %d", runlist_id); + return -EINVAL; + } + + gk20a_dbg_fn("preempt id = %d, runlist_id = %d", id, runlist_id); + + nvgpu_mutex_acquire(&f->runlist_info[runlist_id].mutex); + + mutex_ret = pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + + ret = __locked_fifo_preempt_ch_tsg(g, id, id_type, timeout_rc_type); + + if (!mutex_ret) + pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + + nvgpu_mutex_release(&f->runlist_info[runlist_id].mutex); + + return ret; +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); @@ -346,4 +647,8 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.dump_eng_status = gv11b_dump_eng_status; gops->fifo.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc; gops->fifo.intr_0_error_mask = gv11b_fifo_intr_0_error_mask; + gops->fifo.preempt_channel = gv11b_fifo_preempt_channel; + gops->fifo.preempt_tsg = gv11b_fifo_preempt_tsg; + gops->fifo.is_preempt_pending = gv11b_fifo_is_preempt_pending; + gops->fifo.preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg; } -- cgit v1.2.2 From 40d2f609032a5b492decd0da4c5f50e00f765f37 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 21 Mar 2017 11:22:57 -0700 Subject: gpu: nvgpu: gv11b: implement init_pbdma_intr_desc fifo ops Init device_fatal, channel_fatal and restartable fifo intr pbdma s/w variables for pbdma_intr_0 interrupt masks. pbdma_intr_0 field changes for gv11b:- bit 8(lbreq) does not exists in hw. bit 28 (syncpoint_illegal)is removed in hw. bit 20 is reused for clear_faulted_error in hw. bit 24 (eng_reset) and bit 25 (semaphore) always existed in hw but never handled in s/w. These are added as channel fatal. JIRA GPUT19X-47 Change-Id: I13673430408f1cf7ef762075a29b94196f79a349 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1325401 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 48 ++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b671628a..7e310984 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -624,6 +624,53 @@ static int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, return ret; } +static void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) +{ + /* + * These are all errors which indicate something really wrong + * going on in the device + */ + f->intr.pbdma.device_fatal_0 = + pbdma_intr_0_memreq_pending_f() | + pbdma_intr_0_memack_timeout_pending_f() | + pbdma_intr_0_memack_extra_pending_f() | + pbdma_intr_0_memdat_timeout_pending_f() | + pbdma_intr_0_memdat_extra_pending_f() | + pbdma_intr_0_memflush_pending_f() | + pbdma_intr_0_memop_pending_f() | + pbdma_intr_0_lbconnect_pending_f() | + pbdma_intr_0_lback_timeout_pending_f() | + pbdma_intr_0_lback_extra_pending_f() | + pbdma_intr_0_lbdat_timeout_pending_f() | + pbdma_intr_0_lbdat_extra_pending_f() | + pbdma_intr_0_pri_pending_f(); + + /* + * These are data parsing, framing errors or others which can be + * recovered from with intervention... or just resetting the + * channel + */ + f->intr.pbdma.channel_fatal_0 = + pbdma_intr_0_gpfifo_pending_f() | + pbdma_intr_0_gpptr_pending_f() | + pbdma_intr_0_gpentry_pending_f() | + pbdma_intr_0_gpcrc_pending_f() | + pbdma_intr_0_pbptr_pending_f() | + pbdma_intr_0_pbentry_pending_f() | + pbdma_intr_0_pbcrc_pending_f() | + pbdma_intr_0_method_pending_f() | + pbdma_intr_0_methodcrc_pending_f() | + pbdma_intr_0_pbseg_pending_f() | + pbdma_intr_0_clear_faulted_error_pending_f() | + pbdma_intr_0_eng_reset_pending_f() | + pbdma_intr_0_semaphore_pending_f() | + pbdma_intr_0_signature_pending_f(); + + /* Can be used for sw-methods, or represents a recoverable timeout. */ + f->intr.pbdma.restartable_0 = + pbdma_intr_0_device_pending_f(); +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); @@ -651,4 +698,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.preempt_tsg = gv11b_fifo_preempt_tsg; gops->fifo.is_preempt_pending = gv11b_fifo_is_preempt_pending; gops->fifo.preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg; + gops->fifo.init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs; } -- cgit v1.2.2 From b076c349b26a471776b8c487a702f791e13fb3a4 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 23 Mar 2017 15:25:37 -0700 Subject: gpu: nvgpu: gv11b: fix engine context preempt completion CTX_STATUS_SWITCH: Engine save hasn't started yet, continue to poll CTX_STATUS_INVALID: The engine context has switched off. The preemption step for this engine is complete. CTX_STATUS_VALID or CTX_STATUS_CTXSW_SAVE: check the ID field: * If ID matches the TSG for the context being torn down, the engine reset procedure can be performed, or SW can continue waiting for preempt to finish if id is not being torn down. * If ID does NOT match, the context isn't running on the engine. CTX_STATUS_LOAD: check the NEXT_ID field: * If NEXT_ID matches the TSG of the context being torn down, the engine is loading the context and reset can be performed immediately or after a delay to allow the context a chance to load and be saved off, or sw can continue waiting for preempt to finish if id is not being torn down. * If NEXT_ID does not match the TSG ID or CHID then the context is no longer on the engine. SW may alternatively wait for the CTX_STATUS to reach INVALID, but this may take longer if an unrelated context is currently on the engine or being switched to. JIRA GPUT19X-7 Change-Id: I61499f932019de32e0200084c4c41b21a7cbbd2b Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1327164 Reviewed-by: svccoveritychecker Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 7e310984..1bbf09ec 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -428,27 +428,40 @@ static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, ctx_stat == fifo_engine_status_ctx_status_ctxsw_save_v()) { - if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { - /* called from recovery, eng seems to be hung */ - if (id == fifo_engine_status_id_v(eng_stat)) { + if (id == fifo_engine_status_id_v(eng_stat)) { + if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { + /* called from recovery, eng seems to be hung */ *reset_eng_bitmask |= BIT(engine_idx); ret = 0; break; + } else { + gk20a_dbg_info("wait preempt engine. " + "ctx_status (valid/save)=%u", ctx_stat); } + } else { + /* context is not running on the engine */ + ret = 0; + break; } } else if (ctx_stat == fifo_engine_status_ctx_status_ctxsw_load_v()) { - if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { - /* called from recovery, eng seems to be hung */ - if (id == - fifo_engine_status_next_id_v(eng_stat)) { + if (id == fifo_engine_status_next_id_v(eng_stat)) { + if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { + /* called from recovery, eng seems to be hung */ *reset_eng_bitmask |= BIT(engine_idx); ret = 0; break; + } else { + gk20a_dbg_info("wait preempt engine. " + "ctx_status (load)=%u", ctx_stat); } + } else { + /* context is not running on the engine */ + ret = 0; + break; } } else { -- cgit v1.2.2 From 1bce980d09995947ff59b6d7f39cfaff51a70c74 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 21 Mar 2017 10:00:44 -0700 Subject: gpu: nvgpu: gv11b: init and implement reset_enable_hw -implement gv11b specific reset_enable_hw fifo ops -timeout period in fifo_fb_timeout_r() is set to init instead of max This register specifies the number of microseconds Host should wait for a response from FB before initiating a timeout interrupt. For bringup, this value should be set to a lower value than usual, such as ~.5 milliseconds (500), to help find out bugs in the memory subsystem. -timeout period in pbdma_timeout_r() is set to init instead of max This register contains a value used for detecting timeouts. The timeout value is in microsecond ticks. The timeouts that use this value are: GPfifo fetch timeouts to FB for acks, reqs, rdats. PBDMA connection to LB. GPfifo processor timeouts to FB for acks, reqs, rdats. Method processor timeouts to FB for acks, reqs, rdats. The init value is changed to 64K us based on bug 1816557. JIRA GPUT19X-74 JIRA GPUT19X-47 Change-Id: I6f818e129c3ea67571d206c5e735607cbfcf6ec6 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1325352 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 88 ++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 1bbf09ec..bb9def35 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -29,6 +29,7 @@ #include #include #include +#include #include "fifo_gv11b.h" #include "subctx_gv11b.h" @@ -684,6 +685,92 @@ static void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) pbdma_intr_0_device_pending_f(); } +static u32 gv11b_fifo_intr_0_en_mask(struct gk20a *g) +{ + u32 intr_0_en_mask; + + intr_0_en_mask = g->ops.fifo.intr_0_error_mask(g); + + intr_0_en_mask |= fifo_intr_0_runlist_event_pending_f() | + fifo_intr_0_pbdma_intr_pending_f(); + + return intr_0_en_mask; +} + +int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) +{ + u32 intr_stall; + u32 mask; + u32 timeout; + unsigned int i; + u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA); + + gk20a_dbg_fn(""); + + /* enable pmc pfifo */ + g->ops.mc.reset(g, mc_enable_pfifo_enabled_f()); + + if (g->ops.clock_gating.slcg_ce2_load_gating_prod) + g->ops.clock_gating.slcg_ce2_load_gating_prod(g, + g->slcg_enabled); + if (g->ops.clock_gating.slcg_fifo_load_gating_prod) + g->ops.clock_gating.slcg_fifo_load_gating_prod(g, + g->slcg_enabled); + if (g->ops.clock_gating.blcg_fifo_load_gating_prod) + g->ops.clock_gating.blcg_fifo_load_gating_prod(g, + g->blcg_enabled); + + /* enable pbdma */ + mask = 0; + for (i = 0; i < host_num_pbdma; ++i) + mask |= mc_enable_pb_sel_f(mc_enable_pb_0_enabled_v(), i); + gk20a_writel(g, mc_enable_pb_r(), mask); + + + timeout = gk20a_readl(g, fifo_fb_timeout_r()); + timeout = set_field(timeout, fifo_fb_timeout_period_m(), + fifo_fb_timeout_period_init_f()); + gk20a_dbg_info("fifo_fb_timeout reg val = 0x%08x", timeout); + gk20a_writel(g, fifo_fb_timeout_r(), timeout); + + /* write pbdma timeout value */ + for (i = 0; i < host_num_pbdma; i++) { + timeout = gk20a_readl(g, pbdma_timeout_r(i)); + timeout = set_field(timeout, pbdma_timeout_period_m(), + pbdma_timeout_period_init_f()); + gk20a_dbg_info("pbdma_timeout reg val = 0x%08x", timeout); + gk20a_writel(g, pbdma_timeout_r(i), timeout); + } + /* clear and enable pbdma interrupt */ + for (i = 0; i < host_num_pbdma; i++) { + gk20a_writel(g, pbdma_intr_0_r(i), 0xFFFFFFFF); + gk20a_writel(g, pbdma_intr_1_r(i), 0xFFFFFFFF); + + intr_stall = gk20a_readl(g, pbdma_intr_stall_r(i)); + gk20a_dbg_info("pbdma id:%u, intr_en_0 0x%08x", i, intr_stall); + gk20a_writel(g, pbdma_intr_en_0_r(i), intr_stall); + + intr_stall = gk20a_readl(g, pbdma_intr_stall_1_r(i)); + gk20a_dbg_info("pbdma id:%u, intr_en_1 0x%08x", i, intr_stall); + gk20a_writel(g, pbdma_intr_en_1_r(i), intr_stall); + } + + /* clear runlist interrupts */ + gk20a_writel(g, fifo_intr_runlist_r(), ~0); + + /* clear and enable pfifo interrupt */ + gk20a_writel(g, fifo_intr_0_r(), 0xFFFFFFFF); + mask = gv11b_fifo_intr_0_en_mask(g); + gk20a_dbg_info("fifo_intr_en_0 0x%08x", mask); + gk20a_writel(g, fifo_intr_en_0_r(), mask); + gk20a_dbg_info("fifo_intr_en_1 = 0x80000000"); + gk20a_writel(g, fifo_intr_en_1_r(), 0x80000000); + + gk20a_dbg_fn("done"); + + return 0; +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); @@ -712,4 +799,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.is_preempt_pending = gv11b_fifo_is_preempt_pending; gops->fifo.preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg; gops->fifo.init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs; + gops->fifo.reset_enable_hw = gv11b_init_fifo_reset_enable_hw; } -- cgit v1.2.2 From 3032acfc04f5c483dc08434f27f9912e7dee72c9 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 17 Mar 2017 15:40:34 -0700 Subject: gpu: nvgpu: Move programming of host registers to fifo Move code that touches host registers to fifo HAL. This sorts out some of the dependencies between fifo HAL and channel HAL. Change-Id: I2bff0443ae1c1fa5608e620974b440696d1cfdc4 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1323385 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index bb9def35..2044bb22 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -19,6 +19,7 @@ #include #include "gk20a/gk20a.h" +#include "gk20a/fifo_gk20a.h" #include "gp10b/fifo_gp10b.h" @@ -105,7 +106,8 @@ static void gv11b_userd_writeback_config(struct gk20a *g) } static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, - u64 gpfifo_base, u32 gpfifo_entries, u32 flags) + u64 gpfifo_base, u32 gpfifo_entries, + unsigned long acquire_timeout, u32 flags) { struct gk20a *g = c->g; struct mem_desc *mem = &c->inst_block; @@ -145,7 +147,7 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, pbdma_target_engine_sw_f()); gk20a_mem_wr32(g, mem, ram_fc_acquire_w(), - channel_gk20a_pbdma_acquire_val(c)); + g->ops.fifo.pbdma_acquire_val(acquire_timeout)); gk20a_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(), pbdma_runlist_timeslice_timeout_128_f() | @@ -165,7 +167,7 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, gk20a_mem_wr32(g, mem, ram_fc_config_w(), pbdma_config_auth_level_privileged_f()); - gk20a_channel_setup_ramfc_for_privileged_channel(c); + gk20a_fifo_setup_ramfc_for_privileged_channel(c); } /* Enable userd writeback */ @@ -213,7 +215,7 @@ static void channel_gv11b_unbind(struct channel_gk20a *ch) { gk20a_dbg_fn(""); - channel_gk20a_unbind(ch); + gk20a_fifo_channel_unbind(ch); } static u32 gv11b_fifo_get_num_fifos(struct gk20a *g) -- cgit v1.2.2 From 2766420dfbe15e539a4b9514bbf41480fc636a28 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 16 Mar 2017 15:04:29 -0700 Subject: gpu: nvgpu: gv11b: implement teardown_ch_tsg fifo ops Context TSG teardown procedure: 1. Disable scheduling for the engine's runlist via NV_PFIFO_SCHED_DISABLE. This enables SW to determine whether a context has hung later in the process: otherwise, ongoing work on the runlist may keep ENG_STATUS from reaching a steady state. 2. Disable all channels in the TSG being torn down or submit a new runlist that does not contain the TSG. This is to prevent the TSG from being rescheduled once scheduling is reenabled in step 6. 3. Initiate a preempt of the engine by writing the bit associated with its runlist to NV_PFIFO_RUNLIST_PREEMPT. This allows to begin the preempt process prior to doing the slow register reads needed to determine whether the context has hit any interrupts or is hung. Do not poll NV_PFIFO_RUNLIST_PREEMPT for the preempt to complete. 4. Check for interrupts or hangs while waiting for the preempt to complete. During the pbdma/eng preempt finish polling, any stalling interrupts relating to runlist must be detected and handled in order for the preemption to complete. 5. If a reset is needed as determined by step 4: a. Halt the memory interface for the engine (as per the relevant engine procedure). b. Reset the engine via NV_PMC_ENABLE. c. Take the engine out of reset and reinit the engine (as per relevant engine procedure) 6. Re-enable scheduling for the engine's runlist via NV_PFIFO_SCHED_ENABLE. JIRA GPUT19X-7 Change-Id: I1354dd12b4a4f0e4b4a8d9721581126c02288a85 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1327931 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 370 ++++++++++++++++++++++++++++++++++- 1 file changed, 369 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 2044bb22..57fd24de 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -18,8 +18,10 @@ #include "nvgpu/semaphore.h" #include + #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" +#include "gk20a/ctxsw_trace_gk20a.h" #include "gp10b/fifo_gp10b.h" @@ -360,6 +362,9 @@ static int gv11b_fifo_poll_pbdma_chan_status(struct gk20a *g, u32 id, gk20a_writel(g, pbdma_intr_1_r(pbdma_id), pbdma_intr_1); } + nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), + NVGPU_TIMER_CPU_TIMER); + /* Verify that ch/tsg is no longer on the pbdma */ do { pbdma_stat = gk20a_readl(g, fifo_pbdma_status_r(pbdma_id)); @@ -417,6 +422,9 @@ static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, u32 ctx_stat; int ret = -EBUSY; + nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), + NVGPU_TIMER_CPU_TIMER); + /* Check if ch/tsg has saved off the engine or if ctxsw is hung */ do { eng_stat = gk20a_readl(g, fifo_engine_status_r(engine_idx)); @@ -472,12 +480,153 @@ static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, ret = 0; break; } + usleep_range(delay, delay * 2); + delay = min_t(unsigned long, + delay << 1, GR_IDLE_CHECK_MAX); + } while (!nvgpu_timeout_expired_msg(&timeout, + "preempt timeout eng")); + return ret; +} + +static void gv11b_reset_eng_faulted_ch(struct gk20a *g, u32 hw_chid) +{ + u32 reg_val; + + reg_val = gk20a_readl(g, ccsr_channel_r(hw_chid)); + reg_val |= ccsr_channel_eng_faulted_reset_f(); + gk20a_writel(g, ccsr_channel_r(hw_chid), reg_val); +} + +static void gv11b_reset_eng_faulted_tsg(struct tsg_gk20a *tsg) +{ + struct gk20a *g = tsg->g; + struct channel_gk20a *ch; + + down_read(&tsg->ch_list_lock); + list_for_each_entry(ch, &tsg->ch_list, ch_entry) { + gv11b_reset_eng_faulted_ch(g, ch->hw_chid); + } + up_read(&tsg->ch_list_lock); +} + +static void gv11b_reset_pbdma_faulted_ch(struct gk20a *g, u32 hw_chid) +{ + u32 reg_val; + + reg_val = gk20a_readl(g, ccsr_channel_r(hw_chid)); + reg_val |= ccsr_channel_pbdma_faulted_reset_f(); + gk20a_writel(g, ccsr_channel_r(hw_chid), reg_val); +} + +static void gv11b_reset_pbdma_faulted_tsg(struct tsg_gk20a *tsg) +{ + struct gk20a *g = tsg->g; + struct channel_gk20a *ch; + + down_read(&tsg->ch_list_lock); + list_for_each_entry(ch, &tsg->ch_list, ch_entry) { + gv11b_reset_pbdma_faulted_ch(g, ch->hw_chid); + } + up_read(&tsg->ch_list_lock); +} + +u32 gv11b_fifo_get_runlists_mask(struct gk20a *g, u32 act_eng_bitmask, + u32 id, unsigned int id_type, unsigned int rc_type, + struct mmu_fault_info *mmfault) +{ + u32 runlists_mask = 0; + struct fifo_gk20a *f = &g->fifo; + struct fifo_runlist_info_gk20a *runlist; + u32 pbdma_bitmask = 0; + + if (id_type != ID_TYPE_UNKNOWN) { + if (id_type == ID_TYPE_TSG) + runlists_mask = fifo_sched_disable_runlist_m( + f->tsg[id].runlist_id); + else + runlists_mask = fifo_sched_disable_runlist_m( + f->channel[id].runlist_id); + } else { + if (rc_type == RC_TYPE_MMU_FAULT && mmfault) { + if (mmfault->faulted_pbdma != FIFO_INVAL_PBDMA_ID) + pbdma_bitmask = BIT(mmfault->faulted_pbdma); + + for (id = 0; id < f->max_runlists; id++) { + + runlist = &f->runlist_info[id]; + + if (runlist->eng_bitmask & act_eng_bitmask) + runlists_mask |= + fifo_sched_disable_runlist_m(id); + + if (runlist->pbdma_bitmask & pbdma_bitmask) + runlists_mask |= + fifo_sched_disable_runlist_m(id); + } + } else { + /* ID is unknown */ + for (id = 0; id < f->max_runlists; id++) { + runlist = &f->runlist_info[id]; + if (runlist->eng_bitmask & act_eng_bitmask) + runlists_mask |= + fifo_sched_disable_runlist_m(id); + } + } + } + gk20a_dbg_info("runlists_mask = %08x", runlists_mask); + return runlists_mask; +} + +static void gv11b_fifo_runlist_event_intr_disable(struct gk20a *g) +{ + u32 reg_val; + + reg_val = gk20a_readl(g, fifo_intr_en_0_r()); + reg_val &= fifo_intr_0_runlist_event_pending_f(); + gk20a_writel(g, fifo_intr_en_0_r(), reg_val); +} + +static void gv11b_fifo_runlist_event_intr_enable(struct gk20a *g) +{ + u32 reg_val; + + reg_val = gk20a_readl(g, fifo_intr_en_0_r()); + reg_val |= fifo_intr_0_runlist_event_pending_f(); + gk20a_writel(g, fifo_intr_en_0_r(), reg_val); +} + +static void gv11b_fifo_issue_runlist_preempt(struct gk20a *g, + u32 runlists_mask) +{ + u32 reg_val; + + /* issue runlist preempt */ + reg_val = gk20a_readl(g, fifo_runlist_preempt_r()); + reg_val |= runlists_mask; + gk20a_writel(g, fifo_runlist_preempt_r(), reg_val); +} + +static int gv11b_fifo_poll_runlist_preempt_pending(struct gk20a *g, + u32 runlists_mask) +{ + struct nvgpu_timeout timeout; + u32 delay = GR_IDLE_CHECK_DEFAULT; + int ret = -EBUSY; + + nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), + NVGPU_TIMER_CPU_TIMER); + do { + if (!((gk20a_readl(g, fifo_runlist_preempt_r())) & + runlists_mask)) { + ret = 0; + break; + } usleep_range(delay, delay * 2); delay = min_t(unsigned long, delay << 1, GR_IDLE_CHECK_MAX); } while (!nvgpu_timeout_expired_msg(&timeout, - "preempt timeout engine")); + "runlist preempt timeout")); return ret; } @@ -557,6 +706,31 @@ static int gv11b_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) return ret; } +static int __locked_fifo_preempt_runlists(struct gk20a *g, u32 runlists_mask) +{ + int ret; + + /* + * Disable runlist event interrupt as it will get + * triggered after runlist preempt finishes + */ + gv11b_fifo_runlist_event_intr_disable(g); + + /* issue runlist preempt */ + gv11b_fifo_issue_runlist_preempt(g, runlists_mask); + + /* poll for runlist preempt done */ + ret = gv11b_fifo_poll_runlist_preempt_pending(g, runlists_mask); + + /* Clear outstanding runlist event */ + gk20a_fifo_handle_runlist_event(g); + + /* Enable runlist event interrupt*/ + gv11b_fifo_runlist_event_intr_enable(g); + + return ret; +} + static int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) { struct fifo_gk20a *f = &g->fifo; @@ -584,6 +758,38 @@ static int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) return ret; } + +static int gv11b_fifo_preempt_runlists(struct gk20a *g, u32 runlists_mask) +{ + int ret = 0; + u32 token = PMU_INVALID_MUTEX_OWNER_ID; + u32 mutex_ret = 0; + u32 runlist_id; + + gk20a_dbg_fn(""); + + for (runlist_id = 0; runlist_id < g->fifo.max_runlists; runlist_id++) { + if (runlists_mask & fifo_runlist_preempt_runlist_m(runlist_id)) + nvgpu_mutex_acquire(&g->fifo. + runlist_info[runlist_id].mutex); + } + + mutex_ret = pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + + ret = __locked_fifo_preempt_runlists(g, runlists_mask); + + if (!mutex_ret) + pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + + for (runlist_id = 0; runlist_id < g->fifo.max_runlists; runlist_id++) { + if (runlists_mask & fifo_runlist_preempt_runlist_m(runlist_id)) + nvgpu_mutex_release(&g->fifo. + runlist_info[runlist_id].mutex); + } + + return ret; +} + static int __locked_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, unsigned int id_type, unsigned int timeout_rc_type) { @@ -638,6 +844,167 @@ static int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, nvgpu_mutex_release(&f->runlist_info[runlist_id].mutex); return ret; + +} + +void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, + u32 id, unsigned int id_type, unsigned int rc_type, + struct mmu_fault_info *mmfault) +{ + bool verbose = false; + struct tsg_gk20a *tsg = NULL; + struct channel_gk20a *refch = NULL; + u32 runlists_mask, runlist_id; + struct fifo_runlist_info_gk20a *runlist = NULL; + u32 engine_id, client_type = ~0; + + gk20a_dbg_info("active engine ids bitmask =0x%x", act_eng_bitmask); + gk20a_dbg_info("hw id =%d", id); + gk20a_dbg_info("id_type =%d", id_type); + gk20a_dbg_info("rc_type =%d", rc_type); + gk20a_dbg_info("mmu_fault =%p", mmfault); + + runlists_mask = gv11b_fifo_get_runlists_mask(g, act_eng_bitmask, id, + id_type, rc_type, mmfault); + + gk20a_fifo_set_runlist_state(g, runlists_mask, RUNLIST_DISABLED, + !RUNLIST_INFO_MUTEX_LOCKED); + + g->fifo.deferred_reset_pending = false; + + /* Disable power management */ + if (support_gk20a_pmu(g->dev) && g->elpg_enabled) { + if (gk20a_pmu_disable_elpg(g)) + gk20a_err(dev_from_gk20a(g), + "failed to set disable elpg"); + } + if (g->ops.clock_gating.slcg_gr_load_gating_prod) + g->ops.clock_gating.slcg_gr_load_gating_prod(g, + false); + if (g->ops.clock_gating.slcg_perf_load_gating_prod) + g->ops.clock_gating.slcg_perf_load_gating_prod(g, + false); + if (g->ops.clock_gating.slcg_ltc_load_gating_prod) + g->ops.clock_gating.slcg_ltc_load_gating_prod(g, + false); + + gr_gk20a_init_cg_mode(g, ELCG_MODE, ELCG_RUN); + + if (rc_type == RC_TYPE_MMU_FAULT) + gk20a_debug_dump(g->dev); + + /* get the channel/TSG */ + if (rc_type == RC_TYPE_MMU_FAULT && mmfault && mmfault->refch) { + refch = mmfault->refch; + client_type = mmfault->client_type; + if (gk20a_is_channel_marked_as_tsg(refch)) { + tsg = &g->fifo.tsg[refch->tsgid]; + if (mmfault->faulted_pbdma != FIFO_INVAL_PBDMA_ID) + gv11b_reset_pbdma_faulted_tsg(tsg); + if (mmfault->faulted_engine != FIFO_INVAL_ENGINE_ID) + gv11b_reset_eng_faulted_tsg(tsg); + } else { + if (mmfault->faulted_pbdma != FIFO_INVAL_PBDMA_ID) + gv11b_reset_pbdma_faulted_ch(g, refch->hw_chid); + if (mmfault->faulted_engine != FIFO_INVAL_ENGINE_ID) + gv11b_reset_eng_faulted_ch(g, refch->hw_chid); + } + } else { + if (id_type == ID_TYPE_TSG) + tsg = &g->fifo.tsg[id]; + else if (id_type == ID_TYPE_CHANNEL) + refch = gk20a_channel_get(&g->fifo.channel[id]); + } + + if (id_type == ID_TYPE_TSG || id_type == ID_TYPE_CHANNEL) { + g->ops.fifo.preempt_ch_tsg(g, id, id_type, + PREEMPT_TIMEOUT_NORC); + } else { + gv11b_fifo_preempt_runlists(g, runlists_mask); + } + + if (tsg) { + if (!g->fifo.deferred_reset_pending) { + if (rc_type == RC_TYPE_MMU_FAULT) { + gk20a_fifo_set_ctx_mmu_error_tsg(g, tsg); + verbose = gk20a_fifo_error_tsg(g, tsg); + } + } + gk20a_fifo_abort_tsg(g, tsg->tsgid, false); + if (refch) + gk20a_channel_put(refch); + } else if (refch) { + if (!g->fifo.deferred_reset_pending) { + if (rc_type == RC_TYPE_MMU_FAULT) { + gk20a_fifo_set_ctx_mmu_error_ch(g, refch); + verbose = gk20a_fifo_error_ch(g, refch); + } + } + gk20a_channel_abort(refch, false); + gk20a_channel_put(refch); + } else { + gk20a_err(dev_from_gk20a(g), "id unknown, abort runlist"); + for (runlist_id = 0; runlist_id < g->fifo.max_runlists; + runlist_id++) { + if (runlists_mask & BIT(runlist_id)) + g->ops.fifo.update_runlist(g, runlist_id, + FIFO_INVAL_CHANNEL_ID, false, true); + } + } + + /* check if engine reset should be deferred */ + for (runlist_id = 0; runlist_id < g->fifo.max_runlists; runlist_id++) { + + runlist = &g->fifo.runlist_info[runlist_id]; + if ((runlists_mask & BIT(runlist_id)) && + runlist->reset_eng_bitmask) { + + unsigned long __reset_eng_bitmask = + runlist->reset_eng_bitmask; + + for_each_set_bit(engine_id, &__reset_eng_bitmask, 32) { + if ((refch || tsg) && + gk20a_fifo_should_defer_engine_reset(g, + engine_id, client_type, false)) { + + g->fifo.deferred_fault_engines |= + BIT(engine_id); + + /* handled during channel free */ + g->fifo.deferred_reset_pending = true; + gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, + "sm debugger attached," + " deferring channel recovery to channel free"); + } else { + /* + * if lock is already taken, a reset is + * taking place so no need to repeat + */ + if (nvgpu_mutex_tryacquire( + &g->fifo.gr_reset_mutex)) { + + gk20a_fifo_reset_engine(g, + engine_id); + + nvgpu_mutex_release( + &g->fifo.gr_reset_mutex); + } + } + } + } + } + + if (refch) + gk20a_ctxsw_trace_channel_reset(g, refch); + else if (tsg) + gk20a_ctxsw_trace_tsg_reset(g, tsg); + + gk20a_fifo_set_runlist_state(g, runlists_mask, RUNLIST_ENABLED, + !RUNLIST_INFO_MUTEX_LOCKED); + + /* It is safe to enable ELPG again. */ + if (support_gk20a_pmu(g->dev) && g->elpg_enabled) + gk20a_pmu_enable_elpg(g); } static void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) @@ -802,4 +1169,5 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg; gops->fifo.init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs; gops->fifo.reset_enable_hw = gv11b_init_fifo_reset_enable_hw; + gops->fifo.teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg; } -- cgit v1.2.2 From 633d331ae2db50fbcce829fe324c19fc44b82c24 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Wed, 22 Mar 2017 10:00:24 -0700 Subject: gpu: nvgpu: Rename gk20a_mem_* functions Rename the functions used for mem_desc access to nvgpu_mem_*. JIRA NVGPU-12 Change-Id: I5a1180c9a08d33c3dfc361ce8579c3c767fa5656 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1326193 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 57fd24de..dd56a6f9 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -117,20 +117,20 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, gk20a_dbg_fn(""); - gk20a_memset(g, mem, 0, 0, ram_fc_size_val_v()); + nvgpu_memset(g, mem, 0, 0, ram_fc_size_val_v()); - gk20a_mem_wr32(g, mem, ram_fc_gp_base_w(), + nvgpu_mem_wr32(g, mem, ram_fc_gp_base_w(), pbdma_gp_base_offset_f( u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s()))); - gk20a_mem_wr32(g, mem, ram_fc_gp_base_hi_w(), + nvgpu_mem_wr32(g, mem, ram_fc_gp_base_hi_w(), pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) | pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries))); - gk20a_mem_wr32(g, mem, ram_fc_signature_w(), + nvgpu_mem_wr32(g, mem, ram_fc_signature_w(), c->g->ops.fifo.get_pbdma_signature(c->g)); - gk20a_mem_wr32(g, mem, ram_fc_pb_header_w(), + nvgpu_mem_wr32(g, mem, ram_fc_pb_header_w(), pbdma_pb_header_priv_user_f() | pbdma_pb_header_method_zero_f() | pbdma_pb_header_subchannel_zero_f() | @@ -138,44 +138,44 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, pbdma_pb_header_first_true_f() | pbdma_pb_header_type_inc_f()); - gk20a_mem_wr32(g, mem, ram_fc_subdevice_w(), + nvgpu_mem_wr32(g, mem, ram_fc_subdevice_w(), pbdma_subdevice_id_f(PBDMA_SUBDEVICE_ID) | pbdma_subdevice_status_active_f() | pbdma_subdevice_channel_dma_enable_f()); - gk20a_mem_wr32(g, mem, ram_fc_target_w(), + nvgpu_mem_wr32(g, mem, ram_fc_target_w(), pbdma_target_eng_ctx_valid_true_f() | pbdma_target_ce_ctx_valid_true_f() | pbdma_target_engine_sw_f()); - gk20a_mem_wr32(g, mem, ram_fc_acquire_w(), + nvgpu_mem_wr32(g, mem, ram_fc_acquire_w(), g->ops.fifo.pbdma_acquire_val(acquire_timeout)); - gk20a_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(), + nvgpu_mem_wr32(g, mem, ram_fc_runlist_timeslice_w(), pbdma_runlist_timeslice_timeout_128_f() | pbdma_runlist_timeslice_timescale_3_f() | pbdma_runlist_timeslice_enable_true_f()); - gk20a_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); + nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); /* Until full subcontext is supported, always use VEID0 */ - gk20a_mem_wr32(g, mem, ram_fc_set_channel_info_w(), + nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), pbdma_set_channel_info_scg_type_graphics_compute0_f() | pbdma_set_channel_info_veid_f(CHANNEL_INFO_VEID0)); if (c->is_privileged_channel) { /* Set privilege level for channel */ - gk20a_mem_wr32(g, mem, ram_fc_config_w(), + nvgpu_mem_wr32(g, mem, ram_fc_config_w(), pbdma_config_auth_level_privileged_f()); gk20a_fifo_setup_ramfc_for_privileged_channel(c); } /* Enable userd writeback */ - data = gk20a_mem_rd32(g, mem, ram_fc_config_w()); + data = nvgpu_mem_rd32(g, mem, ram_fc_config_w()); data = data | pbdma_config_userd_writeback_enable_f(); - gk20a_mem_wr32(g, mem, ram_fc_config_w(),data); + nvgpu_mem_wr32(g, mem, ram_fc_config_w(),data); gv11b_userd_writeback_config(g); @@ -196,7 +196,7 @@ static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) struct mem_desc *userd_mem = &g->fifo.userd; u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); - return gk20a_mem_rd32(g, userd_mem, + return nvgpu_mem_rd32(g, userd_mem, offset + ram_userd_gp_get_w()); } @@ -205,7 +205,7 @@ static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) struct mem_desc *userd_mem = &g->fifo.userd; u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); - gk20a_mem_wr32(g, userd_mem, offset + ram_userd_gp_put_w(), + nvgpu_mem_wr32(g, userd_mem, offset + ram_userd_gp_put_w(), c->gpfifo.put); /* commit everything to cpu */ smp_mb(); -- cgit v1.2.2 From c876bec8bab5a1e4d6dea529700ef19c5eac5e64 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Wed, 22 Mar 2017 10:01:14 -0700 Subject: gpu: nvgpu: rename mem_desc to nvgpu_mem $ find -type f | \ xargs sed -i 's/struct mem_desc/struct nvgpu_mem/g' JIRA NVGPU-12 Change-Id: I2b5d015e45185269bfae7c6d4199fe843ff26834 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1326194 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index dd56a6f9..30d695ff 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -112,7 +112,7 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, unsigned long acquire_timeout, u32 flags) { struct gk20a *g = c->g; - struct mem_desc *mem = &c->inst_block; + struct nvgpu_mem *mem = &c->inst_block; u32 data; gk20a_dbg_fn(""); @@ -193,7 +193,7 @@ static void gv11b_ring_channel_doorbell(struct channel_gk20a *c) static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) { - struct mem_desc *userd_mem = &g->fifo.userd; + struct nvgpu_mem *userd_mem = &g->fifo.userd; u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); return nvgpu_mem_rd32(g, userd_mem, @@ -202,7 +202,7 @@ static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) { - struct mem_desc *userd_mem = &g->fifo.userd; + struct nvgpu_mem *userd_mem = &g->fifo.userd; u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); nvgpu_mem_wr32(g, userd_mem, offset + ram_userd_gp_put_w(), -- cgit v1.2.2 From 7fe4b6572ba80dda58d513969b69e22437901077 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 10 Apr 2017 11:09:13 -0700 Subject: gpu: nvgpu: gv11b: Use new error macros gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: I8c0d8944f625e3c5b16a9f5a2a59d95a680f4e55 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1459822 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 30d695ff..3c1982fe 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -875,8 +875,7 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, /* Disable power management */ if (support_gk20a_pmu(g->dev) && g->elpg_enabled) { if (gk20a_pmu_disable_elpg(g)) - gk20a_err(dev_from_gk20a(g), - "failed to set disable elpg"); + nvgpu_err(g, "failed to set disable elpg"); } if (g->ops.clock_gating.slcg_gr_load_gating_prod) g->ops.clock_gating.slcg_gr_load_gating_prod(g, @@ -943,7 +942,7 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, gk20a_channel_abort(refch, false); gk20a_channel_put(refch); } else { - gk20a_err(dev_from_gk20a(g), "id unknown, abort runlist"); + nvgpu_err(g, "id unknown, abort runlist"); for (runlist_id = 0; runlist_id < g->fifo.max_runlists; runlist_id++) { if (runlists_mask & BIT(runlist_id)) -- cgit v1.2.2 From 457f176785af5c8821889d00d89db05bbaf8f772 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 8 Mar 2017 22:34:49 -0800 Subject: gpu: nvgpu: gv11b: init handle sched_error & ctxsw_timout ops - detect and decode sched_error type. Any sched error starting with xxx_* is not supported in h/w and should never be seen by s/w - for bad_tsg sched error, preempt all runlists to recover as faulted ch/tsg is unknown. For other errors, just report error. - ctxsw timeout is not part of sched error fifo interrupt. A new fifo interrupt, ctxsw timeout is added in gv11b. Add s/w handling. Bug 1856152 JIRA GPUT19X-74 Change-Id: I474e1a3cda29a450691fe2ea1dc1e239ce57df1a Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1317615 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 237 ++++++++++++++++++++++++++++++++++- 1 file changed, 234 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 3c1982fe..6883d867 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -15,13 +15,15 @@ #include #include -#include "nvgpu/semaphore.h" +#include #include +#include #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" #include "gk20a/ctxsw_trace_gk20a.h" +#include "gk20a/channel_gk20a.h" #include "gp10b/fifo_gp10b.h" @@ -862,7 +864,7 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, gk20a_dbg_info("hw id =%d", id); gk20a_dbg_info("id_type =%d", id_type); gk20a_dbg_info("rc_type =%d", rc_type); - gk20a_dbg_info("mmu_fault =%p", mmfault); + gk20a_dbg_info("mmu_fault =0x%p", mmfault); runlists_mask = gv11b_fifo_get_runlists_mask(g, act_eng_bitmask, id, id_type, rc_type, mmfault); @@ -1060,7 +1062,8 @@ static u32 gv11b_fifo_intr_0_en_mask(struct gk20a *g) intr_0_en_mask = g->ops.fifo.intr_0_error_mask(g); intr_0_en_mask |= fifo_intr_0_runlist_event_pending_f() | - fifo_intr_0_pbdma_intr_pending_f(); + fifo_intr_0_pbdma_intr_pending_f() | + fifo_intr_0_ctxsw_timeout_pending_f(); return intr_0_en_mask; } @@ -1072,6 +1075,7 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) u32 timeout; unsigned int i; u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA); + struct gk20a_platform *platform = dev_get_drvdata(g->dev); gk20a_dbg_fn(""); @@ -1123,6 +1127,16 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) gk20a_writel(g, pbdma_intr_en_1_r(i), intr_stall); } + /* clear ctxsw timeout interrupts */ + gk20a_writel(g, fifo_intr_ctxsw_timeout_r(), ~0); + + /* enable ctxsw timeout */ + timeout = GRFIFO_TIMEOUT_CHECK_PERIOD_US; + timeout = scale_ptimer(timeout, + ptimer_scalingfactor10x(platform->ptimer_src_freq)); + timeout |= fifo_eng_ctxsw_timeout_detection_enabled_f(); + gk20a_writel(g, fifo_eng_ctxsw_timeout_r(), timeout); + /* clear runlist interrupts */ gk20a_writel(g, fifo_intr_runlist_r(), ~0); @@ -1139,6 +1153,221 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) return 0; } +static const char *const gv11b_sched_error_str[] = { + "xxx-0", + "xxx-1", + "xxx-2", + "xxx-3", + "xxx-4", + "engine_reset", + "rl_ack_timeout", + "rl_ack_extra", + "rl_rdat_timeout", + "rl_rdat_extra", + "xxx-a", + "xxx-b", + "rl_req_timeout", + "new_runlist", + "code_config_while_busy", + "xxx-f", + "xxx-0x10", + "xxx-0x11", + "xxx-0x12", + "xxx-0x13", + "xxx-0x14", + "xxx-0x15", + "xxx-0x16", + "xxx-0x17", + "xxx-0x18", + "xxx-0x19", + "xxx-0x1a", + "xxx-0x1b", + "xxx-0x1c", + "xxx-0x1d", + "xxx-0x1e", + "xxx-0x1f", + "bad_tsg", +}; + +static bool gv11b_fifo_handle_sched_error(struct gk20a *g) +{ + u32 sched_error; + + sched_error = gk20a_readl(g, fifo_intr_sched_error_r()); + + if (sched_error < ARRAY_SIZE(gv11b_sched_error_str)) + nvgpu_err(g, "fifo sched error :%s", + gv11b_sched_error_str[sched_error]); + else + nvgpu_err(g, "fifo sched error code not supported"); + + if (sched_error == SCHED_ERROR_CODE_BAD_TSG ) { + /* id is unknown, preempt all runlists and do recovery */ + gk20a_fifo_recover(g, 0, 0, false, false, false); + } + + return false; +} + +static u32 gv11b_fifo_ctxsw_timeout_info(struct gk20a *g, u32 active_eng_id) +{ + u32 tsgid = FIFO_INVAL_TSG_ID; + u32 timeout_info; + u32 ctx_status, info_status; + + timeout_info = gk20a_readl(g, + fifo_intr_ctxsw_timeout_info_r(active_eng_id)); + + /* + * ctxsw_state and tsgid are snapped at the point of the timeout and + * will not change while the corresponding INTR_CTXSW_TIMEOUT_ENGINE bit + * is PENDING. + */ + ctx_status = fifo_intr_ctxsw_timeout_info_ctxsw_state_v(timeout_info); + if (ctx_status == + fifo_intr_ctxsw_timeout_info_ctxsw_state_load_v()) { + + tsgid = fifo_intr_ctxsw_timeout_info_next_tsgid_v(timeout_info); + + } else if (ctx_status == + fifo_intr_ctxsw_timeout_info_ctxsw_state_switch_v() || + ctx_status == + fifo_intr_ctxsw_timeout_info_ctxsw_state_save_v()) { + + tsgid = fifo_intr_ctxsw_timeout_info_prev_tsgid_v(timeout_info); + } + gk20a_dbg_info("ctxsw timeout info: tsgid = %d", tsgid); + + /* + * STATUS indicates whether the context request ack was eventually + * received and whether a subsequent request timed out. This field is + * updated live while the corresponding INTR_CTXSW_TIMEOUT_ENGINE bit + * is PENDING. STATUS starts in AWAITING_ACK, and progresses to + * ACK_RECEIVED and finally ends with DROPPED_TIMEOUT. + * + * AWAITING_ACK - context request ack still not returned from engine. + * ENG_WAS_RESET - The engine was reset via a PRI write to NV_PMC_ENABLE + * or NV_PMC_ELPG_ENABLE prior to receiving the ack. Host will not + * expect ctx ack to return, but if it is already in flight, STATUS will + * transition shortly to ACK_RECEIVED unless the interrupt is cleared + * first. Once the engine is reset, additional context switches can + * occur; if one times out, STATUS will transition to DROPPED_TIMEOUT + * if the interrupt isn't cleared first. + * ACK_RECEIVED - The ack for the timed-out context request was + * received between the point of the timeout and this register being + * read. Note this STATUS can be reported during the load stage of the + * same context switch that timed out if the timeout occurred during the + * save half of a context switch. Additional context requests may have + * completed or may be outstanding, but no further context timeout has + * occurred. This simplifies checking for spurious context switch + * timeouts. + * DROPPED_TIMEOUT - The originally timed-out context request acked, + * but a subsequent context request then timed out. + * Information about the subsequent timeout is not stored; in fact, that + * context request may also have already been acked by the time SW + * SW reads this register. If not, there is a chance SW can get the + * dropped information by clearing the corresponding + * INTR_CTXSW_TIMEOUT_ENGINE bit and waiting for the timeout to occur + * again. Note, however, that if the engine does time out again, + * it may not be from the original request that caused the + * DROPPED_TIMEOUT state, as that request may + * be acked in the interim. + */ + info_status = fifo_intr_ctxsw_timeout_info_status_v(timeout_info); + if (info_status == + fifo_intr_ctxsw_timeout_info_status_awaiting_ack_v()) { + + gk20a_dbg_info("ctxsw timeout info : awaiting ack"); + + } else if (info_status == + fifo_intr_ctxsw_timeout_info_status_eng_was_reset_v()) { + + gk20a_dbg_info("ctxsw timeout info : eng was reset"); + + } else if (info_status == + fifo_intr_ctxsw_timeout_info_status_ack_received_v()) { + + gk20a_dbg_info("ctxsw timeout info : ack received"); + /* no need to recover */ + tsgid = FIFO_INVAL_TSG_ID; + + } else if (info_status == + fifo_intr_ctxsw_timeout_info_status_dropped_timeout_v()) { + + gk20a_dbg_info("ctxsw timeout info : dropped timeout"); + /* no need to recover */ + tsgid = FIFO_INVAL_TSG_ID; + + } else { + gk20a_dbg_info("ctxsw timeout info status = %u", info_status); + } + + return tsgid; +} + +static bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr) +{ + bool ret = false; + u32 tsgid = FIFO_INVAL_TSG_ID; + u32 engine_id, active_eng_id; + u32 timeout_val, ctxsw_timeout_engines; + + + if (!(fifo_intr & fifo_intr_0_ctxsw_timeout_pending_f())) + return ret; + + /* get ctxsw timedout engines */ + ctxsw_timeout_engines = gk20a_readl(g, fifo_intr_ctxsw_timeout_r()); + if (ctxsw_timeout_engines == 0) { + nvgpu_err(g, "no eng ctxsw timeout pending"); + return ret; + } + + timeout_val = gk20a_readl(g, fifo_eng_ctxsw_timeout_r()); + timeout_val = fifo_eng_ctxsw_timeout_period_v(timeout_val); + + gk20a_dbg_info("eng ctxsw timeout period = 0x%x", timeout_val); + + for (engine_id = 0; engine_id < g->fifo.num_engines; engine_id++) { + active_eng_id = g->fifo.active_engines_list[engine_id]; + + if (ctxsw_timeout_engines & + fifo_intr_ctxsw_timeout_engine_pending_f( + active_eng_id)) { + + struct fifo_gk20a *f = &g->fifo; + u32 ms = 0; + bool verbose = false; + + tsgid = gv11b_fifo_ctxsw_timeout_info(g, active_eng_id); + + if (tsgid == FIFO_INVAL_TSG_ID) + continue; + + if (gk20a_fifo_check_tsg_ctxsw_timeout( + &f->tsg[tsgid], &verbose, &ms)) { + ret = true; + nvgpu_err(g, + "ctxsw timeout error:" + "active engine id =%u, %s=%d, ms=%u", + active_eng_id, "tsg", tsgid, ms); + + /* Cancel all channels' timeout */ + gk20a_channel_timeout_restart_all_channels(g); + gk20a_fifo_recover(g, BIT(active_eng_id), tsgid, + true, true, verbose); + } else { + gk20a_dbg_info( + "fifo is waiting for ctx switch: " + "for %d ms, %s=%d", ms, "tsg", tsgid); + } + } + } + /* clear interrupt */ + gk20a_writel(g, fifo_intr_ctxsw_timeout_r(), ctxsw_timeout_engines); + return ret; +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); @@ -1169,4 +1398,6 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs; gops->fifo.reset_enable_hw = gv11b_init_fifo_reset_enable_hw; gops->fifo.teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg; + gops->fifo.handle_sched_error = gv11b_fifo_handle_sched_error; + gops->fifo.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout; } -- cgit v1.2.2 From 60d0ba2d37b4f2b67ecf0be4d6566af5a289ccb9 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 7 Apr 2017 12:39:10 -0700 Subject: gpu: nvgpu: gv11b: fix *get_runlists_mask* if ch/tsg id is unknown and bit mask for the engines that need to be recovered is not set, runlist mask should correspond to max number of supported runlists JIRA GPUT19X-7 Change-Id: I08e67af0846784a7918510d68de34e9162a42bf6 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1458155 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 45 +++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 19 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 6883d867..d3411d32 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -543,35 +543,42 @@ u32 gv11b_fifo_get_runlists_mask(struct gk20a *g, u32 act_eng_bitmask, if (id_type != ID_TYPE_UNKNOWN) { if (id_type == ID_TYPE_TSG) - runlists_mask = fifo_sched_disable_runlist_m( + runlists_mask |= fifo_sched_disable_runlist_m( f->tsg[id].runlist_id); else - runlists_mask = fifo_sched_disable_runlist_m( + runlists_mask |= fifo_sched_disable_runlist_m( f->channel[id].runlist_id); - } else { - if (rc_type == RC_TYPE_MMU_FAULT && mmfault) { - if (mmfault->faulted_pbdma != FIFO_INVAL_PBDMA_ID) - pbdma_bitmask = BIT(mmfault->faulted_pbdma); + } - for (id = 0; id < f->max_runlists; id++) { + if (rc_type == RC_TYPE_MMU_FAULT && mmfault) { + if (mmfault->faulted_pbdma != FIFO_INVAL_PBDMA_ID) + pbdma_bitmask = BIT(mmfault->faulted_pbdma); - runlist = &f->runlist_info[id]; + for (id = 0; id < f->max_runlists; id++) { - if (runlist->eng_bitmask & act_eng_bitmask) - runlists_mask |= - fifo_sched_disable_runlist_m(id); + runlist = &f->runlist_info[id]; - if (runlist->pbdma_bitmask & pbdma_bitmask) - runlists_mask |= - fifo_sched_disable_runlist_m(id); - } - } else { - /* ID is unknown */ - for (id = 0; id < f->max_runlists; id++) { + if (runlist->eng_bitmask & act_eng_bitmask) + runlists_mask |= + fifo_sched_disable_runlist_m(id); + + if (runlist->pbdma_bitmask & pbdma_bitmask) + runlists_mask |= + fifo_sched_disable_runlist_m(id); + } + } + + if (id_type == ID_TYPE_UNKNOWN) { + for (id = 0; id < f->max_runlists; id++) { + if (act_eng_bitmask) { + /* eng ids are known */ runlist = &f->runlist_info[id]; if (runlist->eng_bitmask & act_eng_bitmask) runlists_mask |= - fifo_sched_disable_runlist_m(id); + fifo_sched_disable_runlist_m(id); + } else { + runlists_mask |= + fifo_sched_disable_runlist_m(id); } } } -- cgit v1.2.2 From 1b4849cda595b5b4e55fdb51e7ecd6c09e1a5fa4 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 16 Feb 2017 16:55:08 -0800 Subject: gpu: nvgpu: gv11b: init pbdma_intr_0 handler Add handling for below two interrupts on top of legacy ones. When pending, PBDMA is stalled and s/w is expected to execute teardown. clear_faulted_error: host is asked to clear fault status when no fault has been asserted. eng_reset: An engine was reset while the PBDMA unit was processing a channel from a runlist which serves the engine. JIRA GPUT19X-47 Change-Id: I776e5799a73a1b63c394048fa61b597e621cf544 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1306558 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index d3411d32..e4dd6a63 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1375,6 +1375,33 @@ static bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr) return ret; } +static unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g, + u32 pbdma_id, u32 pbdma_intr_0, + u32 *handled, u32 *error_notifier) +{ + unsigned int rc_type = RC_TYPE_NO_RC; + + rc_type = gk20a_fifo_handle_pbdma_intr_0(g, pbdma_id, + pbdma_intr_0, handled, error_notifier); + + if (pbdma_intr_0 & pbdma_intr_0_clear_faulted_error_pending_f()) { + gk20a_dbg(gpu_dbg_intr, "clear faulted error on pbdma id %d", + pbdma_id); + gk20a_fifo_reset_pbdma_method(g, pbdma_id, 0); + *handled |= pbdma_intr_0_clear_faulted_error_pending_f(); + rc_type = RC_TYPE_PBDMA_FAULT; + } + + if (pbdma_intr_0 & pbdma_intr_0_eng_reset_pending_f()) { + gk20a_dbg(gpu_dbg_intr, "eng reset intr on pbdma id %d", + pbdma_id); + *handled |= pbdma_intr_0_eng_reset_pending_f(); + rc_type = RC_TYPE_PBDMA_FAULT; + } + + return rc_type; +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); @@ -1407,4 +1434,6 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg; gops->fifo.handle_sched_error = gv11b_fifo_handle_sched_error; gops->fifo.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout; + gops->fifo.handle_pbdma_intr_0 = + gv11b_fifo_handle_pbdma_intr_0; } -- cgit v1.2.2 From be6d308c18d991d4937e6ca467cd41918a3199e8 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Mon, 17 Apr 2017 22:01:23 +0100 Subject: gpu: nvgpu: Move semaphore impl to nvgpu_mem t19x version of similarly named patch in nvgpu. JIRA NVGPU-12 JIRA NVGPU-30 Change-Id: I5b0ce285a25a456d019670fc25b25ed564444643 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1464110 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index e4dd6a63..8346de59 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -280,7 +280,7 @@ static void gv11b_dump_channel_status_ramfc(struct gk20a *g, if (hw_sema) gk20a_debug_output(o, "SEMA STATE: value: 0x%08x " "next_val: 0x%08x addr: 0x%010llx\n", - readl(hw_sema->value), + __nvgpu_semaphore_read(hw_sema), atomic_read(&hw_sema->next_value), nvgpu_hw_sema_addr(hw_sema)); gk20a_debug_output(o, "\n"); -- cgit v1.2.2 From 7fdf02f554a5e922d0cc6797854c5fcfd78bf55f Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 14 Apr 2017 16:10:59 -0700 Subject: gpu: nvgpu: gv11b: Access ptimer_src_freq from gk20a Access ptimer_src_freq from gk20a instead of gk20a_platform. JIRA NVGPU-16 Change-Id: I3f2fcd22eb8a14c83ee2d481ff9f5acdf00f9c07 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1463534 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 8346de59..f16fbb98 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1082,7 +1082,6 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) u32 timeout; unsigned int i; u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA); - struct gk20a_platform *platform = dev_get_drvdata(g->dev); gk20a_dbg_fn(""); @@ -1140,7 +1139,7 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) /* enable ctxsw timeout */ timeout = GRFIFO_TIMEOUT_CHECK_PERIOD_US; timeout = scale_ptimer(timeout, - ptimer_scalingfactor10x(platform->ptimer_src_freq)); + ptimer_scalingfactor10x(g->ptimer_src_freq)); timeout |= fifo_eng_ctxsw_timeout_detection_enabled_f(); gk20a_writel(g, fifo_eng_ctxsw_timeout_r(), timeout); -- cgit v1.2.2 From 92895a57a733cffe9f4318be9a5064c9e32350e1 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 27 Apr 2017 11:02:41 -0700 Subject: gpu: nvgpu: gv11b: fix error for static code analysis Functions that are not declared in header files are made static Bug 200299572 Change-Id: Ibf9e9cc9f48ad9ceaa202d1bb7ed57724057cda0 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1471538 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index f16fbb98..421ccd15 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -532,7 +532,7 @@ static void gv11b_reset_pbdma_faulted_tsg(struct tsg_gk20a *tsg) up_read(&tsg->ch_list_lock); } -u32 gv11b_fifo_get_runlists_mask(struct gk20a *g, u32 act_eng_bitmask, +static u32 gv11b_fifo_get_runlists_mask(struct gk20a *g, u32 act_eng_bitmask, u32 id, unsigned int id_type, unsigned int rc_type, struct mmu_fault_info *mmfault) { @@ -639,7 +639,7 @@ static int gv11b_fifo_poll_runlist_preempt_pending(struct gk20a *g, return ret; } -int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, +static int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, unsigned int id_type, unsigned int timeout_rc_type) { struct fifo_gk20a *f = &g->fifo; @@ -856,7 +856,7 @@ static int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, } -void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, +static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, u32 id, unsigned int id_type, unsigned int rc_type, struct mmu_fault_info *mmfault) { @@ -1075,7 +1075,7 @@ static u32 gv11b_fifo_intr_0_en_mask(struct gk20a *g) return intr_0_en_mask; } -int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) +static int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) { u32 intr_stall; u32 mask; -- cgit v1.2.2 From 10540e3915d9be82863d8472e31a2683a8f73097 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 14 Apr 2017 16:13:04 -0700 Subject: gpu: nvgpu: gv11b: Use new support_pmu flag Use new gk20a->support_pmu flag instead of using the old support_gk20a_pmu() macro. The latter depends on access to Linux device structure. JIRA NVGPU-16 Change-Id: I6b843305b15b29893a1e3b0d60f37c44bdb3b2cb Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1463535 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 421ccd15..df7ab5af 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -882,7 +882,7 @@ static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, g->fifo.deferred_reset_pending = false; /* Disable power management */ - if (support_gk20a_pmu(g->dev) && g->elpg_enabled) { + if (g->support_pmu && g->elpg_enabled) { if (gk20a_pmu_disable_elpg(g)) nvgpu_err(g, "failed to set disable elpg"); } @@ -1011,7 +1011,7 @@ static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, !RUNLIST_INFO_MUTEX_LOCKED); /* It is safe to enable ELPG again. */ - if (support_gk20a_pmu(g->dev) && g->elpg_enabled) + if (g->support_pmu && g->elpg_enabled) gk20a_pmu_enable_elpg(g); } -- cgit v1.2.2 From a5fc5e7131add41f2d9b4bbba2a9d0f318897331 Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Mon, 22 May 2017 12:20:40 +0300 Subject: gpu: nvgpu: gv11b: implement userd_pb_get Add gv11b_userd_pb_get() to read the userd get pointer for watchdog. Jira NVGPU-72 Change-Id: Ie1cdb9f84edcecd70b44b6e5a6a8bc554ad5bf49 Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/1486956 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index df7ab5af..a153de7c 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -202,6 +202,16 @@ static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) offset + ram_userd_gp_get_w()); } +static u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c) +{ + struct nvgpu_mem *userd_mem = &g->fifo.userd; + u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); + u32 lo = nvgpu_mem_rd32(g, userd_mem, offset + ram_userd_get_w()); + u32 hi = nvgpu_mem_rd32(g, userd_mem, offset + ram_userd_get_hi_w()); + + return ((u64)hi << 32) | lo; +} + static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) { struct nvgpu_mem *userd_mem = &g->fifo.userd; @@ -1412,6 +1422,7 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.get_num_fifos = gv11b_fifo_get_num_fifos; gops->fifo.userd_gp_get = gv11b_userd_gp_get; gops->fifo.userd_gp_put = gv11b_userd_gp_put; + gops->fifo.userd_pb_get = gv11b_userd_pb_get; gops->fifo.setup_ramfc = channel_gv11b_setup_ramfc; gops->fifo.resetup_ramfc = NULL; gops->fifo.unbind_channel = channel_gv11b_unbind; -- cgit v1.2.2 From 1f78355c5c909e2f678a60420c0abd8ec5adbc98 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 22 Nov 2016 09:09:39 -0800 Subject: gpu: nvgpu: gv11b: add support for sync points In t19x, host1x supports sync point through memory mapped shim layer. So sync-point operations implemented through semphore methods signaling to this sync-point shim layer. Added relevant hal functions for this in fifo hal. JIRA GPUT19X-2 Change-Id: Ia514637d046ba093f4e5afa6cbd06673672fd189 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1258235 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 136 ++++++++++++++++++++++++++++++++++- 1 file changed, 135 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index a153de7c..4b4c97b4 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -14,11 +14,17 @@ */ #include #include +#ifdef CONFIG_TEGRA_GK20A_NVHOST +#include +#include +#endif #include #include #include - +#include +#include +#include #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -1411,6 +1417,123 @@ static unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g, return rc_type; } +#ifdef CONFIG_TEGRA_GK20A_NVHOST +static int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, + u32 syncpt_id, struct nvgpu_mem *syncpt_buf) +{ + struct page **pages; + u32 nr_pages; + u32 i; + int err = 0; + struct gk20a *g = c->g; + + /* + * Add rw mapping for entire syncpt shim for current channel vm + * TODO : This needs to replaced with a new mecahnism where + * only current syncpoint range will be rw and other sync + * points range is read only for current channel vm. Also share + * these mapping accross channels if they share same vm + */ + nr_pages = DIV_ROUND_UP(g->syncpt_unit_size, PAGE_SIZE); + pages = nvgpu_kzalloc(g, sizeof(struct page *) * nr_pages); + for (i = 0; i < nr_pages; i++) + pages[i] = phys_to_page(g->syncpt_unit_base + + PAGE_SIZE * i); + __nvgpu_mem_create_from_pages(g, syncpt_buf, pages, nr_pages); + nvgpu_kfree(g, pages); + syncpt_buf->gpu_va = nvgpu_gmmu_map(c->vm, syncpt_buf, + g->syncpt_unit_size, 0, gk20a_mem_flag_none, + false, APERTURE_SYSMEM); + + if (!syncpt_buf->gpu_va) { + nvgpu_err(c->g, "failed to map syncpt buffer"); + nvgpu_dma_free(c->g, syncpt_buf); + err = -ENOMEM; + } + return err; +} + +static void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c, + struct nvgpu_mem *syncpt_buf) +{ + nvgpu_gmmu_unmap(c->vm, syncpt_buf, syncpt_buf->gpu_va); + nvgpu_dma_free(c->g, syncpt_buf); +} + +static void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, + struct priv_cmd_entry *cmd, u32 off, + u32 id, u32 thresh, u64 gpu_va_base) +{ + u64 gpu_va = gpu_va_base + + nvhost_syncpt_unit_interface_get_byte_offset(id); + + gk20a_dbg_fn(""); + + off = cmd->off + off; + + /* semaphore_a */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010004); + nvgpu_mem_wr32(g, cmd->mem, off++, + (gpu_va >> 32) & 0xff); + /* semaphore_b */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010005); + /* offset */ + nvgpu_mem_wr32(g, cmd->mem, off++, gpu_va & 0xffffffff); + + /* semaphore_c */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006); + /* payload */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x0); + /* semaphore_d */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007); + /* operation: acq_geq, switch_en */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x4 | (0x1 << 12)); +} + +static u32 gv11b_fifo_get_syncpt_wait_cmd_size(void) +{ + return 8; +} + +static void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, + bool wfi_cmd, struct priv_cmd_entry *cmd, + u32 id, u64 gpu_va_base) +{ + u32 off = cmd->off; + u64 gpu_va = gpu_va_base + + nvhost_syncpt_unit_interface_get_byte_offset(id); + + gk20a_dbg_fn(""); + + /* semaphore_a */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010004); + nvgpu_mem_wr32(g, cmd->mem, off++, + (gpu_va >> 32) & 0xff); + /* semaphore_b */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010005); + /* offset */ + nvgpu_mem_wr32(g, cmd->mem, off++, gpu_va & 0xffffffff); + + /* semaphore_c */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006); + /* payload */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x0); + /* semaphore_d */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007); + + /* operation: release, wfi */ + nvgpu_mem_wr32(g, cmd->mem, off++, + 0x2 | ((wfi_cmd ? 0x0 : 0x1) << 20)); + /* ignored */ + nvgpu_mem_wr32(g, cmd->mem, off++, 0); +} + +static u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd) +{ + return 9; +} +#endif /* CONFIG_TEGRA_GK20A_NVHOST */ + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); @@ -1446,4 +1569,15 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout; gops->fifo.handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0; +#ifdef CONFIG_TEGRA_GK20A_NVHOST + gops->fifo.alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf; + gops->fifo.free_syncpt_buf = gv11b_fifo_free_syncpt_buf; + gops->fifo.add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd; + gops->fifo.get_syncpt_wait_cmd_size = + gv11b_fifo_get_syncpt_wait_cmd_size; + gops->fifo.add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd; + gops->fifo.get_syncpt_incr_cmd_size = + gv11b_fifo_get_syncpt_incr_cmd_size; +#endif + } -- cgit v1.2.2 From b28e43f62bc600b0505d66d6d00d4a6ea6591744 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 22 May 2017 14:53:37 -0700 Subject: gpu: nvgpu: gv11b: fifo ops get_mmu_fault_info set to NULL mmu fault h/w registers are no longer inside fifo module JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: I7d166f0e80cee7c040289b13a053ff2cdb7d8727 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1487327 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 4b4c97b4..38a402dc 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1554,6 +1554,7 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v; gops->fifo.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc; gops->fifo.trigger_mmu_fault = NULL; + gops->fifo.get_mmu_fault_info = NULL; gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status; gops->fifo.dump_eng_status = gv11b_dump_eng_status; gops->fifo.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc; -- cgit v1.2.2 From 39727398230bdb0fb01d9aa54e4cc572f6d39299 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 24 May 2017 13:27:28 -0700 Subject: gpu: nvgpu: gv11b: No need to set init val for fb & pbdma timeout fb_timeout and pbdma_timeout values are already set by h/w to init values. No need to reinitialize. JIRA GPUT19X-22 Change-Id: If6f1111f58940d51e53f028b046c42fa852221ee Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1493458 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 38a402dc..b6691db5 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -1122,19 +1123,13 @@ static int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) timeout = gk20a_readl(g, fifo_fb_timeout_r()); - timeout = set_field(timeout, fifo_fb_timeout_period_m(), - fifo_fb_timeout_period_init_f()); - gk20a_dbg_info("fifo_fb_timeout reg val = 0x%08x", timeout); - gk20a_writel(g, fifo_fb_timeout_r(), timeout); - - /* write pbdma timeout value */ + nvgpu_log_info(g, "fifo_fb_timeout reg val = 0x%08x", timeout); for (i = 0; i < host_num_pbdma; i++) { timeout = gk20a_readl(g, pbdma_timeout_r(i)); - timeout = set_field(timeout, pbdma_timeout_period_m(), - pbdma_timeout_period_init_f()); - gk20a_dbg_info("pbdma_timeout reg val = 0x%08x", timeout); - gk20a_writel(g, pbdma_timeout_r(i), timeout); + nvgpu_log_info(g, "pbdma_timeout reg val = 0x%08x", + timeout); } + /* clear and enable pbdma interrupt */ for (i = 0; i < host_num_pbdma; i++) { gk20a_writel(g, pbdma_intr_0_r(i), 0xFFFFFFFF); -- cgit v1.2.2 From 66d0c84f3ca42ab2453a71b850d9a2a4c556fdff Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 30 May 2017 19:50:40 +0530 Subject: gpu: nvgpu: use correct parameters for gk20a_debug_dump() Pass struct gk20a * pointer instead of device pointer to gk20a_debug_dump() API This patch is needed since definition of gk20a_debug_dump() has changed Jira NVGPU-62 Change-Id: I7e67f6b792e575ee72eb6a5b0f7c53e5122a545f Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1492113 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b6691db5..367d61f5 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -916,7 +916,7 @@ static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, gr_gk20a_init_cg_mode(g, ELCG_MODE, ELCG_RUN); if (rc_type == RC_TYPE_MMU_FAULT) - gk20a_debug_dump(g->dev); + gk20a_debug_dump(g); /* get the channel/TSG */ if (rc_type == RC_TYPE_MMU_FAULT && mmfault && mmfault->refch) { -- cgit v1.2.2 From 8da78a9fa7826985e8ca08a0a15eb1d6f38a222e Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 31 May 2017 13:29:06 +0530 Subject: gpu: nvgpu: include Include explicitly wherever the debug operations are used Jira NVGPU-62 Change-Id: I1845e08774b7c211e7fd954937708905f905e069 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1492818 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 367d61f5..2bd72d51 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -26,6 +26,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" -- cgit v1.2.2 From 65f0c731695265f1b1b08d7c43a6778aa0300117 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 1 Jun 2017 16:15:04 -0700 Subject: gpu: nvgpu: gv11b: payload for syncpt wait Program payload for sync point wait command. JIRA GPUT19X-2 Change-Id: I1a8e0176a056aa1c7008761f8b253ec17b5703c2 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1494353 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 2bd72d51..0dd0fc40 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1479,7 +1479,7 @@ static void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, /* semaphore_c */ nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010006); /* payload */ - nvgpu_mem_wr32(g, cmd->mem, off++, 0x0); + nvgpu_mem_wr32(g, cmd->mem, off++, thresh); /* semaphore_d */ nvgpu_mem_wr32(g, cmd->mem, off++, 0x20010007); /* operation: acq_geq, switch_en */ -- cgit v1.2.2 From 5205ab23a29d6bb2d94eecae67ba344f438c5045 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 2 Jun 2017 14:51:08 +0530 Subject: gpu: nvgpu: use nvgpu specific nvhost APIs Remove use of linux specifix header files and and use nvgpu specific header file instead This is needed to remove all Linux dependencies from nvgpu driver Replace all nvhost_*() calls by nvgpu_nvhost_*() calls from new nvgpu library Jira NVGPU-29 Change-Id: I32d59628ca5ab3ece80a10eb5aefa150b1da448b Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1494648 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 0dd0fc40..b018f3d9 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -14,10 +14,6 @@ */ #include #include -#ifdef CONFIG_TEGRA_GK20A_NVHOST -#include -#include -#endif #include #include @@ -27,6 +23,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -1461,7 +1458,7 @@ static void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, u32 id, u32 thresh, u64 gpu_va_base) { u64 gpu_va = gpu_va_base + - nvhost_syncpt_unit_interface_get_byte_offset(id); + nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(id); gk20a_dbg_fn(""); @@ -1497,7 +1494,7 @@ static void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, { u32 off = cmd->off; u64 gpu_va = gpu_va_base + - nvhost_syncpt_unit_interface_get_byte_offset(id); + nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(id); gk20a_dbg_fn(""); -- cgit v1.2.2 From 002d6f147490cd5b3002ce5a564f4276df784ea6 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 10 May 2017 17:18:01 +0530 Subject: gpu: nvgpu: PMU IPC reorg support update - prepend PMU IPC func with nvgpu_ by replacing gk20a_ - updated gv11b HAL methods of queue & mutex to point to gk20a HAL methods. JIRA NVGPU-56 Change-Id: Iade9f5613dbd4bc11515e822ddfda3a1787bfa4f Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1479117 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b018f3d9..847bf172 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -718,12 +718,12 @@ static int gv11b_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) nvgpu_mutex_acquire(&f->runlist_info[runlist_id].mutex); - mutex_ret = pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); ret = __locked_fifo_preempt(g, hw_chid, false); if (!mutex_ret) - pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); nvgpu_mutex_release(&f->runlist_info[runlist_id].mutex); @@ -770,12 +770,12 @@ static int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) nvgpu_mutex_acquire(&f->runlist_info[runlist_id].mutex); - mutex_ret = pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); ret = __locked_fifo_preempt(g, tsgid, true); if (!mutex_ret) - pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); nvgpu_mutex_release(&f->runlist_info[runlist_id].mutex); @@ -798,12 +798,12 @@ static int gv11b_fifo_preempt_runlists(struct gk20a *g, u32 runlists_mask) runlist_info[runlist_id].mutex); } - mutex_ret = pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); ret = __locked_fifo_preempt_runlists(g, runlists_mask); if (!mutex_ret) - pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); for (runlist_id = 0; runlist_id < g->fifo.max_runlists; runlist_id++) { if (runlists_mask & fifo_runlist_preempt_runlist_m(runlist_id)) @@ -858,12 +858,12 @@ static int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, nvgpu_mutex_acquire(&f->runlist_info[runlist_id].mutex); - mutex_ret = pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); ret = __locked_fifo_preempt_ch_tsg(g, id, id_type, timeout_rc_type); if (!mutex_ret) - pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); nvgpu_mutex_release(&f->runlist_info[runlist_id].mutex); -- cgit v1.2.2 From 4f0e19d44dee9039378bce7bd0cfb11f36fd8926 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 7 Jun 2017 13:17:22 -0700 Subject: gpu: nvgpu: gv11b: issue tsg preempt only Preempt type should be set to tsg and id should be set to tsgid in fifo_preempt_r(). Preempt type channel and id set to channel id does not initiate preemption. Bug 200289427 Bug 200292090 Bug 200289491 Change-Id: I2ae96c0b9ca8a88a8405f42775744f0879994887 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1497877 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 35 +++++++++++++---------------------- 1 file changed, 13 insertions(+), 22 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 847bf172..90295f52 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -706,28 +706,13 @@ static int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, static int gv11b_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) { struct fifo_gk20a *f = &g->fifo; - u32 ret = 0; - u32 token = PMU_INVALID_MUTEX_OWNER_ID; - u32 mutex_ret = 0; - u32 runlist_id; - - gk20a_dbg_fn("%d", hw_chid); - - runlist_id = f->channel[hw_chid].runlist_id; - gk20a_dbg_fn("runlist_id %d", runlist_id); - - nvgpu_mutex_acquire(&f->runlist_info[runlist_id].mutex); - - mutex_ret = nvgpu_pmu_mutex_acquire(&g->pmu, PMU_MUTEX_ID_FIFO, &token); - - ret = __locked_fifo_preempt(g, hw_chid, false); - - if (!mutex_ret) - nvgpu_pmu_mutex_release(&g->pmu, PMU_MUTEX_ID_FIFO, &token); + u32 tsgid; - nvgpu_mutex_release(&f->runlist_info[runlist_id].mutex); + tsgid = f->channel[hw_chid].tsgid; + nvgpu_log_info(g, "chid:%d tsgid:%d", hw_chid, tsgid); - return ret; + /* Preempt tsg. Channel preempt is NOOP */ + return g->ops.fifo.preempt_tsg(g, tsgid); } static int __locked_fifo_preempt_runlists(struct gk20a *g, u32 runlists_mask) @@ -818,9 +803,15 @@ static int __locked_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, unsigned int id_type, unsigned int timeout_rc_type) { int ret; + struct fifo_gk20a *f = &g->fifo; - /* issue preempt */ - gk20a_fifo_issue_preempt(g, id, id_type); + nvgpu_log_fn(g, "id:%d id_type:%d", id, id_type); + + /* Issue tsg preempt. Channel preempt is noop */ + if (id_type == ID_TYPE_CHANNEL) + gk20a_fifo_issue_preempt(g, f->channel[id].tsgid, true); + else + gk20a_fifo_issue_preempt(g, id, true); /* wait for preempt */ ret = g->ops.fifo.is_preempt_pending(g, id, id_type, -- cgit v1.2.2 From e50d046ab4354a990d304316630d6aac3c4e9d76 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 8 Jun 2017 15:49:18 +0530 Subject: gpu: nvgpu: PMU PG reorg support update - Prepend ELPG enable/disable methods with nvgpu_ by replacing gk20a_ in gv11b JIRA NVGPU-97 Change-Id: I8900f7635e30578040afa71e0bd470ee835a4748 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1498400 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 90295f52..a86a9509 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -889,7 +889,7 @@ static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, /* Disable power management */ if (g->support_pmu && g->elpg_enabled) { - if (gk20a_pmu_disable_elpg(g)) + if (nvgpu_pmu_disable_elpg(g)) nvgpu_err(g, "failed to set disable elpg"); } if (g->ops.clock_gating.slcg_gr_load_gating_prod) @@ -1018,7 +1018,7 @@ static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, /* It is safe to enable ELPG again. */ if (g->support_pmu && g->elpg_enabled) - gk20a_pmu_enable_elpg(g); + nvgpu_pmu_enable_elpg(g); } static void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) -- cgit v1.2.2 From f500f45ebf7c658d67ec6001d2e88105d7e3f875 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 22 Jun 2017 16:31:27 -0700 Subject: gpu: nvgpu: gv11b: implement ctxnotvalid pbdma_intr_1 Pbdma which encountered the ctxnotvalid interrupt will stall and prevent the channel which was loaded at the time the interrupt fired from being swapped out until the interrupt is cleared. CTXNOTVALID pbdma interrupt indicates error conditions related to the *_CTX_VALID fields for a channel. The following conditions trigger the interrupt: * CTX_VALID bit for the targeted engine is FALSE * At channel start/resume, all preemptible eng have CTX_VALID FALSE but: - CTX_RELOAD is set in CCSR_CHANNEL_STATUS, - PBDMA_TARGET_SHOULD_SEND_HOST_TSG_EVENT is TRUE, or - PBDMA_TARGET_NEEDS_HOST_TSG_EVENT is TRUE JIRA GPUT19X-47 Change-Id: If65ce1fcdbaebd6b1d8313fdddf9e3e0fa51e885 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1329372 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 59 ++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index a86a9509..5425eaa0 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1401,6 +1401,63 @@ static unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g, return rc_type; } +/* + * Pbdma which encountered the ctxnotvalid interrupt will stall and + * prevent the channel which was loaded at the time the interrupt fired + * from being swapped out until the interrupt is cleared. + * CTXNOTVALID pbdma interrupt indicates error conditions related + * to the *_CTX_VALID fields for a channel. The following + * conditions trigger the interrupt: + * * CTX_VALID bit for the targeted engine is FALSE + * * At channel start/resume, all preemptible eng have CTX_VALID FALSE but: + * - CTX_RELOAD is set in CCSR_CHANNEL_STATUS, + * - PBDMA_TARGET_SHOULD_SEND_HOST_TSG_EVENT is TRUE, or + * - PBDMA_TARGET_NEEDS_HOST_TSG_EVENT is TRUE + * The field is left NOT_PENDING and the interrupt is not raised if the PBDMA is + * currently halted. This allows SW to unblock the PBDMA and recover. + * SW may read METHOD0, CHANNEL_STATUS and TARGET to determine whether the + * interrupt was due to an engine method, CTX_RELOAD, SHOULD_SEND_HOST_TSG_EVENT + * or NEEDS_HOST_TSG_EVENT. If METHOD0 VALID is TRUE, lazy context creation + * can be used or the TSG may be destroyed. + * If METHOD0 VALID is FALSE, the error is likely a bug in SW, and the TSG + * will have to be destroyed. + */ + +static unsigned int gv11b_fifo_handle_pbdma_intr_1(struct gk20a *g, + u32 pbdma_id, u32 pbdma_intr_1, + u32 *handled, u32 *error_notifier) +{ + unsigned int rc_type = RC_TYPE_PBDMA_FAULT; + u32 pbdma_intr_1_current = gk20a_readl(g, pbdma_intr_1_r(pbdma_id)); + + /* minimize race with the gpu clearing the pending interrupt */ + if (!(pbdma_intr_1_current & + pbdma_intr_1_ctxnotvalid_pending_f())) + pbdma_intr_1 &= ~pbdma_intr_1_ctxnotvalid_pending_f(); + + if (pbdma_intr_1 == 0) + return RC_TYPE_NO_RC; + + if (pbdma_intr_1 & pbdma_intr_1_ctxnotvalid_pending_f()) { + gk20a_dbg(gpu_dbg_intr, "ctxnotvalid intr on pbdma id %d", + pbdma_id); + nvgpu_err(g, "pbdma_intr_1(%d)= 0x%08x ", + pbdma_id, pbdma_intr_1); + *handled |= pbdma_intr_1_ctxnotvalid_pending_f(); + } else{ + /* + * rest of the interrupts in _intr_1 are "host copy engine" + * related, which is not supported. For now just make them + * channel fatal. + */ + nvgpu_err(g, "hce err: pbdma_intr_1(%d):0x%08x", + pbdma_id, pbdma_intr_1); + *handled |= pbdma_intr_1; + } + + return rc_type; +} + #ifdef CONFIG_TEGRA_GK20A_NVHOST static int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, u32 syncpt_id, struct nvgpu_mem *syncpt_buf) @@ -1554,6 +1611,8 @@ void gv11b_init_fifo(struct gpu_ops *gops) gops->fifo.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout; gops->fifo.handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0; + gops->fifo.handle_pbdma_intr_1 = + gv11b_fifo_handle_pbdma_intr_1; #ifdef CONFIG_TEGRA_GK20A_NVHOST gops->fifo.alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf; gops->fifo.free_syncpt_buf = gv11b_fifo_free_syncpt_buf; -- cgit v1.2.2 From e1655282238b4632c2af4ac809d81b297d5183f2 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Tue, 27 Jun 2017 11:15:41 -0700 Subject: gpu: nvgpu: gv11b: rename hw_chid to chid hw_chid is a relative id for vgpu. For native it's same as hw id. Renaming it to chid to avoid confusing. Jira VFND-3796 Change-Id: Ie94c1a15e9e45fc823d85790ce6a69da53a685bf Signed-off-by: Richard Zhao Reviewed-on: https://git-master/r/1509531 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 48 ++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 24 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 5425eaa0..dbde2fed 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -99,7 +99,7 @@ static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) addr_hi = u64_hi32(gk20a_mm_inst_block_addr(g, &c->inst_block)); runlist[2] = ram_rl_entry_chan_inst_ptr_lo_f(addr_lo) | - ram_rl_entry_chid_f(c->hw_chid); + ram_rl_entry_chid_f(c->chid); runlist[3] = ram_rl_entry_chan_inst_ptr_hi_f(addr_hi); gk20a_dbg_info("gv11b channel runlist [0] %x [1] %x [2] %x [3] %x\n", @@ -164,7 +164,7 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, pbdma_runlist_timeslice_enable_true_f()); - nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); + nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); /* Until full subcontext is supported, always use VEID0 */ nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), @@ -192,16 +192,16 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, static void gv11b_ring_channel_doorbell(struct channel_gk20a *c) { - gk20a_dbg_info("channel ring door bell %d\n", c->hw_chid); + gk20a_dbg_info("channel ring door bell %d\n", c->chid); gk20a_writel(c->g, usermode_notify_channel_pending_r(), - usermode_notify_channel_pending_id_f(c->hw_chid)); + usermode_notify_channel_pending_id_f(c->chid)); } static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) { struct nvgpu_mem *userd_mem = &g->fifo.userd; - u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); + u32 offset = c->chid * (g->fifo.userd_entry_size / sizeof(u32)); return nvgpu_mem_rd32(g, userd_mem, offset + ram_userd_gp_get_w()); @@ -210,7 +210,7 @@ static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) static u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c) { struct nvgpu_mem *userd_mem = &g->fifo.userd; - u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); + u32 offset = c->chid * (g->fifo.userd_entry_size / sizeof(u32)); u32 lo = nvgpu_mem_rd32(g, userd_mem, offset + ram_userd_get_w()); u32 hi = nvgpu_mem_rd32(g, userd_mem, offset + ram_userd_get_hi_w()); @@ -220,7 +220,7 @@ static u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c) static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) { struct nvgpu_mem *userd_mem = &g->fifo.userd; - u32 offset = c->hw_chid * (g->fifo.userd_entry_size / sizeof(u32)); + u32 offset = c->chid * (g->fifo.userd_entry_size / sizeof(u32)); nvgpu_mem_wr32(g, userd_mem, offset + ram_userd_gp_put_w(), c->gpfifo.put); @@ -249,13 +249,13 @@ static bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid) static void gv11b_dump_channel_status_ramfc(struct gk20a *g, struct gk20a_debug_output *o, - u32 hw_chid, + u32 chid, struct ch_state *ch_state) { - u32 channel = gk20a_readl(g, ccsr_channel_r(hw_chid)); + u32 channel = gk20a_readl(g, ccsr_channel_r(chid)); u32 status = ccsr_channel_status_v(channel); u32 *inst_mem; - struct channel_gk20a *c = g->fifo.channel + hw_chid; + struct channel_gk20a *c = g->fifo.channel + chid; struct nvgpu_semaphore_int *hw_sema = NULL; if (c->hw_sema) @@ -266,7 +266,7 @@ static void gv11b_dump_channel_status_ramfc(struct gk20a *g, inst_mem = &ch_state->inst_block[0]; - gk20a_debug_output(o, "%d-%s, pid %d, refs: %d: ", hw_chid, + gk20a_debug_output(o, "%d-%s, pid %d, refs: %d: ", chid, dev_name(g->dev), ch_state->pid, ch_state->refs); @@ -505,13 +505,13 @@ static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, return ret; } -static void gv11b_reset_eng_faulted_ch(struct gk20a *g, u32 hw_chid) +static void gv11b_reset_eng_faulted_ch(struct gk20a *g, u32 chid) { u32 reg_val; - reg_val = gk20a_readl(g, ccsr_channel_r(hw_chid)); + reg_val = gk20a_readl(g, ccsr_channel_r(chid)); reg_val |= ccsr_channel_eng_faulted_reset_f(); - gk20a_writel(g, ccsr_channel_r(hw_chid), reg_val); + gk20a_writel(g, ccsr_channel_r(chid), reg_val); } static void gv11b_reset_eng_faulted_tsg(struct tsg_gk20a *tsg) @@ -521,18 +521,18 @@ static void gv11b_reset_eng_faulted_tsg(struct tsg_gk20a *tsg) down_read(&tsg->ch_list_lock); list_for_each_entry(ch, &tsg->ch_list, ch_entry) { - gv11b_reset_eng_faulted_ch(g, ch->hw_chid); + gv11b_reset_eng_faulted_ch(g, ch->chid); } up_read(&tsg->ch_list_lock); } -static void gv11b_reset_pbdma_faulted_ch(struct gk20a *g, u32 hw_chid) +static void gv11b_reset_pbdma_faulted_ch(struct gk20a *g, u32 chid) { u32 reg_val; - reg_val = gk20a_readl(g, ccsr_channel_r(hw_chid)); + reg_val = gk20a_readl(g, ccsr_channel_r(chid)); reg_val |= ccsr_channel_pbdma_faulted_reset_f(); - gk20a_writel(g, ccsr_channel_r(hw_chid), reg_val); + gk20a_writel(g, ccsr_channel_r(chid), reg_val); } static void gv11b_reset_pbdma_faulted_tsg(struct tsg_gk20a *tsg) @@ -542,7 +542,7 @@ static void gv11b_reset_pbdma_faulted_tsg(struct tsg_gk20a *tsg) down_read(&tsg->ch_list_lock); list_for_each_entry(ch, &tsg->ch_list, ch_entry) { - gv11b_reset_pbdma_faulted_ch(g, ch->hw_chid); + gv11b_reset_pbdma_faulted_ch(g, ch->chid); } up_read(&tsg->ch_list_lock); } @@ -703,13 +703,13 @@ static int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, return ret; } -static int gv11b_fifo_preempt_channel(struct gk20a *g, u32 hw_chid) +static int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid) { struct fifo_gk20a *f = &g->fifo; u32 tsgid; - tsgid = f->channel[hw_chid].tsgid; - nvgpu_log_info(g, "chid:%d tsgid:%d", hw_chid, tsgid); + tsgid = f->channel[chid].tsgid; + nvgpu_log_info(g, "chid:%d tsgid:%d", chid, tsgid); /* Preempt tsg. Channel preempt is NOOP */ return g->ops.fifo.preempt_tsg(g, tsgid); @@ -919,9 +919,9 @@ static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, gv11b_reset_eng_faulted_tsg(tsg); } else { if (mmfault->faulted_pbdma != FIFO_INVAL_PBDMA_ID) - gv11b_reset_pbdma_faulted_ch(g, refch->hw_chid); + gv11b_reset_pbdma_faulted_ch(g, refch->chid); if (mmfault->faulted_engine != FIFO_INVAL_ENGINE_ID) - gv11b_reset_eng_faulted_ch(g, refch->hw_chid); + gv11b_reset_eng_faulted_ch(g, refch->chid); } } else { if (id_type == ID_TYPE_TSG) -- cgit v1.2.2 From 7346122ae66d35a39ebbdcb423de5bfc4fb66f4e Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Tue, 27 Jun 2017 16:50:28 -0700 Subject: gpu: nvgpu: gv11b: add fifo_gv11b and usermode_regs - add fifo_gv11b to store usermode_regs - consider channel_base and use usermode_regs when ring channel doorbell It'll make kickoff code re-usable for vgpu. Jira VFND-3796 Change-Id: Ia6974ccac137f201ad8763a7d372de81d5cca56b Signed-off-by: Richard Zhao Reviewed-on: https://git-master/r/1510457 Reviewed-by: Aingara Paramakuru GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index dbde2fed..1194663b 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -48,6 +48,15 @@ #define CHANNEL_INFO_VEID0 0 #define PBDMA_SUBDEVICE_ID 1 +static inline void gv11b_usermode_writel(struct gk20a *g, u32 r, u32 v) +{ + struct fifo_gk20a *f = &g->fifo; + void __iomem *reg = f->t19x.usermode_regs + (r - usermode_cfg0_r()); + + writel_relaxed(v, reg); + gk20a_dbg(gpu_dbg_reg, "usermode r=0x%x v=0x%x", r, v); +} + static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) { @@ -192,10 +201,13 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, static void gv11b_ring_channel_doorbell(struct channel_gk20a *c) { + struct fifo_gk20a *f = &c->g->fifo; + u32 hw_chid = f->channel_base + c->chid; + gk20a_dbg_info("channel ring door bell %d\n", c->chid); - gk20a_writel(c->g, usermode_notify_channel_pending_r(), - usermode_notify_channel_pending_id_f(c->chid)); + gv11b_usermode_writel(c->g, usermode_notify_channel_pending_r(), + usermode_notify_channel_pending_id_f(hw_chid)); } static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) @@ -1575,11 +1587,19 @@ static u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd) } #endif /* CONFIG_TEGRA_GK20A_NVHOST */ +static int gv11b_init_fifo_setup_hw(struct gk20a *g) +{ + struct fifo_gk20a *f = &g->fifo; + + f->t19x.usermode_regs = g->regs + usermode_cfg0_r(); + return 0; +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); /* for gv11b no need to do any thing special for fifo hw setup */ - gops->fifo.init_fifo_setup_hw = NULL; + gops->fifo.init_fifo_setup_hw = gv11b_init_fifo_setup_hw; gops->fifo.runlist_entry_size = ram_rl_entry_size_v; gops->fifo.get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry; gops->fifo.get_ch_runlist_entry = gv11b_get_ch_runlist_entry; -- cgit v1.2.2 From 8a0221cfc735f79c94447ff5922e26c313e0f177 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 27 Jun 2017 16:36:48 -0700 Subject: gpu: nvgpu: gv11b: implement eng method buffer init/deinit When CE hits a page fault it needs to save out methods, it will save it out to a per runqueue per TSG method buffer. The method buffers (one per TSG runqueue) are allocated in BAR2 space during TSG creation All channels in a TSG that are mapped to the same runqueue will point to the same buffer. S/w will insert channel's method buffer pointer in the channel's instance block entries NV_RAMIN_ENG_METHOD_BUFFER_ADDR_LO and NV_RAMIN_ENG_METHOD_BUFFER_ADDR_HI. Method buffer in memory will be 32B aligned. Eng method buffer allocated per tsg will be de-allocated during tsg_release. JIRA GPUT19X-46 Change-Id: Ib480ae5840d9815d24fe2eadc169ac3102854cd0 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1509747 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 109 +++++++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 1194663b..3e73a29e 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -48,6 +48,9 @@ #define CHANNEL_INFO_VEID0 0 #define PBDMA_SUBDEVICE_ID 1 +static void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g, + struct channel_gk20a *ch, struct nvgpu_mem *mem); + static inline void gv11b_usermode_writel(struct gk20a *g, u32 r, u32 v) { struct fifo_gk20a *f = &g->fifo; @@ -180,6 +183,8 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, pbdma_set_channel_info_scg_type_graphics_compute0_f() | pbdma_set_channel_info_veid_f(CHANNEL_INFO_VEID0)); + gv11b_fifo_init_ramfc_eng_method_buffer(g, c, mem); + if (c->is_privileged_channel) { /* Set privilege level for channel */ nvgpu_mem_wr32(g, mem, ram_fc_config_w(), @@ -1470,6 +1475,106 @@ static unsigned int gv11b_fifo_handle_pbdma_intr_1(struct gk20a *g, return rc_type; } +static void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g, + struct channel_gk20a *ch, struct nvgpu_mem *mem) +{ + struct tsg_gk20a *tsg; + struct nvgpu_mem *method_buffer_per_runque; + + tsg = tsg_gk20a_from_ch(ch); + if (tsg == NULL) { + nvgpu_err(g, "channel is not part of tsg"); + return; + } + if (tsg->eng_method_buffers == NULL) { + nvgpu_log_info(g, "eng method buffer NULL"); + return; + } + if (tsg->runlist_id == gk20a_fifo_get_fast_ce_runlist_id(g)) + method_buffer_per_runque = + &tsg->eng_method_buffers[ASYNC_CE_RUNQUE]; + else + method_buffer_per_runque = + &tsg->eng_method_buffers[GR_RUNQUE]; + + nvgpu_mem_wr32(g, mem, ram_in_eng_method_buffer_addr_lo_w(), + u64_lo32(method_buffer_per_runque->gpu_va)); + nvgpu_mem_wr32(g, mem, ram_in_eng_method_buffer_addr_hi_w(), + u64_hi32(method_buffer_per_runque->gpu_va)); + + nvgpu_log_info(g, "init ramfc with method buffer"); +} + +unsigned int gv11b_fifo_get_eng_method_buffer_size(struct gk20a *g) +{ + unsigned int buffer_size; + + buffer_size = ((9 + 1 + 3) * g->ops.ce2.get_num_pce(g)) + 2; + buffer_size = (27 * 5 * buffer_size); + buffer_size = roundup(buffer_size, PAGE_SIZE); + nvgpu_log_info(g, "method buffer size in bytes %d", buffer_size); + + return buffer_size; +} + +static void gv11b_fifo_init_eng_method_buffers(struct gk20a *g, + struct tsg_gk20a *tsg) +{ + struct vm_gk20a *vm = g->mm.bar2.vm; + int err = 0; + unsigned int i, runque, method_buffer_size; + unsigned int num_pbdma = g->fifo.num_pbdma; + + if (tsg->eng_method_buffers != NULL) + return; + + method_buffer_size = gv11b_fifo_get_eng_method_buffer_size(g); + if (method_buffer_size == 0) { + nvgpu_info(g, "ce will hit MTHD_BUFFER_FAULT"); + return; + } + + tsg->eng_method_buffers = nvgpu_kzalloc(g, + num_pbdma * sizeof(struct nvgpu_mem)); + + for (runque = 0; runque < num_pbdma; runque++) { + err = nvgpu_dma_alloc_map_sys(vm, method_buffer_size, + &tsg->eng_method_buffers[runque]); + if (err) + break; + } + if (err) { + for (i = runque; i < runque; i--) + nvgpu_dma_unmap_free(vm, + &tsg->eng_method_buffers[runque]); + + nvgpu_kfree(g, tsg->eng_method_buffers); + tsg->eng_method_buffers = NULL; + nvgpu_err(g, "could not alloc eng method buffers"); + return; + } + nvgpu_log_info(g, "eng method buffers allocated"); + +} + +static void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g, + struct tsg_gk20a *tsg) +{ + struct vm_gk20a *vm = g->mm.bar2.vm; + unsigned int runque; + + if (tsg->eng_method_buffers == NULL) + return; + + for (runque = 0; runque < g->fifo.num_pbdma; runque++) + nvgpu_dma_unmap_free(vm, &tsg->eng_method_buffers[runque]); + + nvgpu_kfree(g, tsg->eng_method_buffers); + tsg->eng_method_buffers = NULL; + + nvgpu_log_info(g, "eng method buffers de-allocated"); +} + #ifdef CONFIG_TEGRA_GK20A_NVHOST static int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, u32 syncpt_id, struct nvgpu_mem *syncpt_buf) @@ -1633,6 +1738,10 @@ void gv11b_init_fifo(struct gpu_ops *gops) gv11b_fifo_handle_pbdma_intr_0; gops->fifo.handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1; + gops->fifo.init_eng_method_buffers = + gv11b_fifo_init_eng_method_buffers; + gops->fifo.deinit_eng_method_buffers = + gv11b_fifo_deinit_eng_method_buffers; #ifdef CONFIG_TEGRA_GK20A_NVHOST gops->fifo.alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf; gops->fifo.free_syncpt_buf = gv11b_fifo_free_syncpt_buf; -- cgit v1.2.2 From 5cda5a3074e4c7dae1857e1dfdf55017b0450786 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 27 Jun 2017 22:10:49 -0700 Subject: gpu: nvgpu: gv11b: add a function to reset pbdma and eng faulted When Host receives a page fault signal from a CE, Host will immediately set _ENG_FAULTED bit in the NV_PCCSR_CHANNEL register for the channel and will trigger a preempt of the TSG/channel. A channel will only be scheduled when _ENABLED=1, _ENG_FAULTED=0 and _PBDMA_FAULTED=0 in pccsr_channel reg for the channel. If a TSG has a faulted channel, Host will not schedule the entire TSG agin until all _FAULTED bits from channels in the TSG are cleared by SW. This function will be required for ce page fault handling. JIRA GPUT19X-46 JIRA GPUT19X-12 Change-Id: Ib58dff7aa24aa144e970f11b5261877dec03f3e6 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1509776 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 38 +++++++++++++++++++++++++----------- 1 file changed, 27 insertions(+), 11 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 3e73a29e..a1f6d258 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -564,6 +564,29 @@ static void gv11b_reset_pbdma_faulted_tsg(struct tsg_gk20a *tsg) up_read(&tsg->ch_list_lock); } +void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g, + struct channel_gk20a *refch, + u32 faulted_pbdma, u32 faulted_engine) +{ + struct tsg_gk20a *tsg; + + nvgpu_log(g, gpu_dbg_intr, "reset faulted pbdma:0x%x eng:0x%x", + faulted_pbdma, faulted_engine); + + if (gk20a_is_channel_marked_as_tsg(refch)) { + tsg = &g->fifo.tsg[refch->tsgid]; + if (faulted_pbdma != FIFO_INVAL_PBDMA_ID) + gv11b_reset_pbdma_faulted_tsg(tsg); + if (faulted_engine != FIFO_INVAL_ENGINE_ID) + gv11b_reset_eng_faulted_tsg(tsg); + } else { + if (faulted_pbdma != FIFO_INVAL_PBDMA_ID) + gv11b_reset_pbdma_faulted_ch(g, refch->chid); + if (faulted_engine != FIFO_INVAL_ENGINE_ID) + gv11b_reset_eng_faulted_ch(g, refch->chid); + } +} + static u32 gv11b_fifo_get_runlists_mask(struct gk20a *g, u32 act_eng_bitmask, u32 id, unsigned int id_type, unsigned int rc_type, struct mmu_fault_info *mmfault) @@ -928,18 +951,11 @@ static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, if (rc_type == RC_TYPE_MMU_FAULT && mmfault && mmfault->refch) { refch = mmfault->refch; client_type = mmfault->client_type; - if (gk20a_is_channel_marked_as_tsg(refch)) { + if (gk20a_is_channel_marked_as_tsg(refch)) tsg = &g->fifo.tsg[refch->tsgid]; - if (mmfault->faulted_pbdma != FIFO_INVAL_PBDMA_ID) - gv11b_reset_pbdma_faulted_tsg(tsg); - if (mmfault->faulted_engine != FIFO_INVAL_ENGINE_ID) - gv11b_reset_eng_faulted_tsg(tsg); - } else { - if (mmfault->faulted_pbdma != FIFO_INVAL_PBDMA_ID) - gv11b_reset_pbdma_faulted_ch(g, refch->chid); - if (mmfault->faulted_engine != FIFO_INVAL_ENGINE_ID) - gv11b_reset_eng_faulted_ch(g, refch->chid); - } + gv11b_fifo_reset_pbdma_and_eng_faulted(g, refch, + mmfault->faulted_pbdma, + mmfault->faulted_engine); } else { if (id_type == ID_TYPE_TSG) tsg = &g->fifo.tsg[id]; -- cgit v1.2.2 From 6d758eb81bcbff4e50df5c9fa67a369a4e1f2074 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 29 Jun 2017 15:59:05 -0700 Subject: gpu: nvgpu: gv11b: support for full subcontext Changes to enable 64 subcontexts: 1 SYNC + 63 ASYNC Currently all subcontexts with in a tsg can have only single address space. Add support for NVGPU_TSG_IOCTL_BIND_CHANNEL_EX for selecting subctx id by client. Bug 1842197 Change-Id: Icf56a41303bd1ad7fc6f2a6fbc691bb7b4a01d22 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master/r/1511145 Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index a1f6d258..ace873e9 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -45,7 +45,6 @@ #include "subctx_gv11b.h" #include "gr_gv11b.h" -#define CHANNEL_INFO_VEID0 0 #define PBDMA_SUBDEVICE_ID 1 static void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g, @@ -94,7 +93,8 @@ static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) /* Time being use 0 pbdma sequencer */ runlist_entry = ram_rl_entry_type_channel_v() | - ram_rl_entry_chan_runqueue_selector_f(0) | + ram_rl_entry_chan_runqueue_selector_f( + c->t19x.runqueue_sel) | ram_rl_entry_chan_userd_target_f( ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()) | ram_rl_entry_chan_inst_target_f( @@ -178,10 +178,14 @@ static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); - /* Until full subcontext is supported, always use VEID0 */ - nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), - pbdma_set_channel_info_scg_type_graphics_compute0_f() | - pbdma_set_channel_info_veid_f(CHANNEL_INFO_VEID0)); + if (c->t19x.subctx_id == CHANNEL_INFO_VEID0) + nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), + pbdma_set_channel_info_scg_type_graphics_compute0_f() | + pbdma_set_channel_info_veid_f(c->t19x.subctx_id)); + else + nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), + pbdma_set_channel_info_scg_type_compute1_f() | + pbdma_set_channel_info_veid_f(c->t19x.subctx_id)); gv11b_fifo_init_ramfc_eng_method_buffer(g, c, mem); -- cgit v1.2.2 From efd9ba3a797ee5b7edf4fb9464c802d3d5d29b68 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Sun, 2 Jul 2017 12:59:28 -0700 Subject: gpu: nvgpu: gv11b: Use g->name instead of dev_name() Dump device name using g->name instead of dev_name(). dev_name() is Linux specific. Change-Id: I65eb89e41ca81ca6143fb247a10c306b4efc96ad Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master/r/1512176 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index ace873e9..b0d182dc 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -288,7 +288,7 @@ static void gv11b_dump_channel_status_ramfc(struct gk20a *g, inst_mem = &ch_state->inst_block[0]; gk20a_debug_output(o, "%d-%s, pid %d, refs: %d: ", chid, - dev_name(g->dev), + g->name, ch_state->pid, ch_state->refs); gk20a_debug_output(o, "channel status: %s in use %s %s\n", @@ -333,7 +333,7 @@ static void gv11b_dump_eng_status(struct gk20a *g, u32 status = gk20a_readl(g, fifo_engine_status_r(i)); u32 ctx_status = fifo_engine_status_ctx_status_v(status); - gk20a_debug_output(o, "%s eng %d: ", dev_name(g->dev), i); + gk20a_debug_output(o, "%s eng %d: ", g->name, i); gk20a_debug_output(o, "id: %d (%s), next_id: %d (%s), ctx status: %s ", fifo_engine_status_id_v(status), -- cgit v1.2.2 From 2f6d321390a98ace1e52f21c6a399e06b3fe71e7 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 7 Mar 2017 12:16:07 -0800 Subject: gpu: nvgpu: gv11b: add mmu fault handling HUB reports following memory sub-system interrupts: a) ACCESS_COUNTER_NOTIFY: GET != PUT for access counter notify buffer b) ACCESS_COUNTER_ERROR: HUB received a NACK (BAR2 fault) when writing the notify buffer out to memory c) MMU_ECC_UNCORRECTED_ERROR_NOTIFY: Uncorrected ECC error detected by HUB MMU d) MMU_REPLAYABLE_FAULT_NOTIFY: GET != PUT for replayable fault buffer e) MMU_REPLAYABLE_FAULT_OVERFLOW: Overflow when writing to the replayable fault buffer f) MMU_NONREPLAYABLE_FAULT_NOTIFY: GET != PUT for non-replayable fault buffer g) MMU_NONREPLAYABLE_FAULT_OVERFLOW: Overflow when writing to the non-replayable fault buffer h) MMU_OTHER_FAULT_NOTIFY: All other fault notifications from MMU This change is to : -Detect other fault notify -Copy fault info from fault snap register for other fault notify interrupt -Detect and handle nonreplay/replay fault notify and fault overflow -Copy fault info from fault buffer for nonreplay/replay fault -Print fault info JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: Ifa08a4ebcd119a7d81c2eae3f52dc825d1ce3898 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1493394 Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 71 ++++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b0d182dc..b0270150 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1720,6 +1720,77 @@ static int gv11b_init_fifo_setup_hw(struct gk20a *g) return 0; } +static u32 gv11b_mmu_fault_id_to_gr_veid(struct gk20a *g, u32 gr_eng_fault_id, + u32 mmu_fault_id) +{ + u32 num_subctx; + u32 veid = FIFO_INVAL_VEID; + + num_subctx = gv11b_get_max_subctx_count(g); + + if (mmu_fault_id >= gr_eng_fault_id && + mmu_fault_id < (gr_eng_fault_id + num_subctx)) + veid = mmu_fault_id - gr_eng_fault_id; + + return veid; +} + +static u32 gv11b_mmu_fault_id_to_eng_id_and_veid(struct gk20a *g, + u32 mmu_fault_id, u32 *veid) +{ + u32 engine_id; + u32 active_engine_id; + struct fifo_engine_info_gk20a *engine_info; + struct fifo_gk20a *f = &g->fifo; + + + for (engine_id = 0; engine_id < f->num_engines; engine_id++) { + active_engine_id = f->active_engines_list[engine_id]; + engine_info = &g->fifo.engine_info[active_engine_id]; + + if (active_engine_id == ENGINE_GR_GK20A) { + /* get faulted subctx id */ + *veid = gv11b_mmu_fault_id_to_gr_veid(g, + engine_info->fault_id, mmu_fault_id); + if (*veid != FIFO_INVAL_VEID) + break; + } else { + if (engine_info->fault_id == mmu_fault_id) + break; + } + + active_engine_id = FIFO_INVAL_ENGINE_ID; + } + return active_engine_id; +} + +static u32 gv11b_mmu_fault_id_to_pbdma_id(struct gk20a *g, u32 mmu_fault_id) +{ + u32 num_pbdma, reg_val, fault_id_pbdma0; + + reg_val = gk20a_readl(g, fifo_cfg0_r()); + num_pbdma = fifo_cfg0_num_pbdma_v(reg_val); + fault_id_pbdma0 = fifo_cfg0_pbdma_fault_id_v(reg_val); + + if (mmu_fault_id >= fault_id_pbdma0 && + mmu_fault_id <= fault_id_pbdma0 + num_pbdma - 1) + return mmu_fault_id - fault_id_pbdma0; + + return FIFO_INVAL_PBDMA_ID; +} + +void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g, + u32 mmu_fault_id, u32 *active_engine_id, u32 *veid, u32 *pbdma_id) +{ + *active_engine_id = gv11b_mmu_fault_id_to_eng_id_and_veid(g, + mmu_fault_id, veid); + + if (*active_engine_id == FIFO_INVAL_ENGINE_ID) + *pbdma_id = gv11b_mmu_fault_id_to_pbdma_id(g, mmu_fault_id); + else + *pbdma_id = FIFO_INVAL_PBDMA_ID; +} + void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); -- cgit v1.2.2 From 8140c51e6cd212517fc343e6f8f8694bbad98f3b Mon Sep 17 00:00:00 2001 From: Sunny He Date: Fri, 30 Jun 2017 15:54:03 -0700 Subject: gpu: nvgpu: gv11b: Reorg fifo HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fifo sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I7c81edfa785a4ecafef41aae7b82d6b1707d294e Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1522554 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 119 ++++++++++------------------------- 1 file changed, 32 insertions(+), 87 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b0270150..e210d40d 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -59,7 +59,7 @@ static inline void gv11b_usermode_writel(struct gk20a *g, u32 r, u32 v) gk20a_dbg(gpu_dbg_reg, "usermode r=0x%x v=0x%x", r, v); } -static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) +void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) { u32 runlist_entry_0 = ram_rl_entry_type_tsg_v(); @@ -85,7 +85,7 @@ static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) } -static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) +void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) { struct gk20a *g = c->g; u32 addr_lo, addr_hi; @@ -126,7 +126,7 @@ static void gv11b_userd_writeback_config(struct gk20a *g) } -static int channel_gv11b_setup_ramfc(struct channel_gk20a *c, +int channel_gv11b_setup_ramfc(struct channel_gk20a *c, u64 gpfifo_base, u32 gpfifo_entries, unsigned long acquire_timeout, u32 flags) { @@ -219,7 +219,7 @@ static void gv11b_ring_channel_doorbell(struct channel_gk20a *c) usermode_notify_channel_pending_id_f(hw_chid)); } -static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) +u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) { struct nvgpu_mem *userd_mem = &g->fifo.userd; u32 offset = c->chid * (g->fifo.userd_entry_size / sizeof(u32)); @@ -228,7 +228,7 @@ static u32 gv11b_userd_gp_get(struct gk20a *g, struct channel_gk20a *c) offset + ram_userd_gp_get_w()); } -static u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c) +u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c) { struct nvgpu_mem *userd_mem = &g->fifo.userd; u32 offset = c->chid * (g->fifo.userd_entry_size / sizeof(u32)); @@ -238,7 +238,7 @@ static u64 gv11b_userd_pb_get(struct gk20a *g, struct channel_gk20a *c) return ((u64)hi << 32) | lo; } -static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) +void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) { struct nvgpu_mem *userd_mem = &g->fifo.userd; u32 offset = c->chid * (g->fifo.userd_entry_size / sizeof(u32)); @@ -251,24 +251,24 @@ static void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) gv11b_ring_channel_doorbell(c); } -static void channel_gv11b_unbind(struct channel_gk20a *ch) +void channel_gv11b_unbind(struct channel_gk20a *ch) { gk20a_dbg_fn(""); gk20a_fifo_channel_unbind(ch); } -static u32 gv11b_fifo_get_num_fifos(struct gk20a *g) +u32 gv11b_fifo_get_num_fifos(struct gk20a *g) { return ccsr_channel__size_1_v(); } -static bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid) +bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid) { return (engine_subid == gmmu_fault_client_type_gpc_v()); } -static void gv11b_dump_channel_status_ramfc(struct gk20a *g, +void gv11b_dump_channel_status_ramfc(struct gk20a *g, struct gk20a_debug_output *o, u32 chid, struct ch_state *ch_state) @@ -322,7 +322,7 @@ static void gv11b_dump_channel_status_ramfc(struct gk20a *g, gk20a_debug_output(o, "\n"); } -static void gv11b_dump_eng_status(struct gk20a *g, +void gv11b_dump_eng_status(struct gk20a *g, struct gk20a_debug_output *o) { u32 i, host_num_engines; @@ -355,7 +355,7 @@ static void gv11b_dump_eng_status(struct gk20a *g, gk20a_debug_output(o, "\n"); } -static u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g) +u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g) { u32 intr_0_error_mask = fifo_intr_0_bind_error_pending_f() | @@ -698,7 +698,7 @@ static int gv11b_fifo_poll_runlist_preempt_pending(struct gk20a *g, return ret; } -static int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, +int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, unsigned int id_type, unsigned int timeout_rc_type) { struct fifo_gk20a *f = &g->fifo; @@ -747,7 +747,7 @@ static int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, return ret; } -static int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid) +int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid) { struct fifo_gk20a *f = &g->fifo; u32 tsgid; @@ -784,7 +784,7 @@ static int __locked_fifo_preempt_runlists(struct gk20a *g, u32 runlists_mask) return ret; } -static int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) +int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) { struct fifo_gk20a *f = &g->fifo; u32 ret = 0; @@ -868,7 +868,7 @@ static int __locked_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, } -static int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, +int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, unsigned int id_type, unsigned int timeout_rc_type) { struct fifo_gk20a *f = &g->fifo; @@ -906,7 +906,7 @@ static int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, } -static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, +void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, u32 id, unsigned int id_type, unsigned int rc_type, struct mmu_fault_info *mmfault) { @@ -1058,7 +1058,7 @@ static void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, nvgpu_pmu_enable_elpg(g); } -static void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) +void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) { /* * These are all errors which indicate something really wrong @@ -1118,7 +1118,7 @@ static u32 gv11b_fifo_intr_0_en_mask(struct gk20a *g) return intr_0_en_mask; } -static int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) +int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) { u32 intr_stall; u32 mask; @@ -1232,7 +1232,7 @@ static const char *const gv11b_sched_error_str[] = { "bad_tsg", }; -static bool gv11b_fifo_handle_sched_error(struct gk20a *g) +bool gv11b_fifo_handle_sched_error(struct gk20a *g) { u32 sched_error; @@ -1348,7 +1348,7 @@ static u32 gv11b_fifo_ctxsw_timeout_info(struct gk20a *g, u32 active_eng_id) return tsgid; } -static bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr) +bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr) { bool ret = false; u32 tsgid = FIFO_INVAL_TSG_ID; @@ -1411,7 +1411,7 @@ static bool gv11b_fifo_handle_ctxsw_timeout(struct gk20a *g, u32 fifo_intr) return ret; } -static unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g, +unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_0, u32 *handled, u32 *error_notifier) { @@ -1460,7 +1460,7 @@ static unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g, * will have to be destroyed. */ -static unsigned int gv11b_fifo_handle_pbdma_intr_1(struct gk20a *g, +unsigned int gv11b_fifo_handle_pbdma_intr_1(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_1, u32 *handled, u32 *error_notifier) { @@ -1537,7 +1537,7 @@ unsigned int gv11b_fifo_get_eng_method_buffer_size(struct gk20a *g) return buffer_size; } -static void gv11b_fifo_init_eng_method_buffers(struct gk20a *g, +void gv11b_fifo_init_eng_method_buffers(struct gk20a *g, struct tsg_gk20a *tsg) { struct vm_gk20a *vm = g->mm.bar2.vm; @@ -1577,7 +1577,7 @@ static void gv11b_fifo_init_eng_method_buffers(struct gk20a *g, } -static void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g, +void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g, struct tsg_gk20a *tsg) { struct vm_gk20a *vm = g->mm.bar2.vm; @@ -1596,7 +1596,7 @@ static void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g, } #ifdef CONFIG_TEGRA_GK20A_NVHOST -static int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, +int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, u32 syncpt_id, struct nvgpu_mem *syncpt_buf) { struct page **pages; @@ -1631,14 +1631,14 @@ static int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, return err; } -static void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c, +void gv11b_fifo_free_syncpt_buf(struct channel_gk20a *c, struct nvgpu_mem *syncpt_buf) { nvgpu_gmmu_unmap(c->vm, syncpt_buf, syncpt_buf->gpu_va); nvgpu_dma_free(c->g, syncpt_buf); } -static void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, +void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, struct priv_cmd_entry *cmd, u32 off, u32 id, u32 thresh, u64 gpu_va_base) { @@ -1668,12 +1668,12 @@ static void gv11b_fifo_add_syncpt_wait_cmd(struct gk20a *g, nvgpu_mem_wr32(g, cmd->mem, off++, 0x4 | (0x1 << 12)); } -static u32 gv11b_fifo_get_syncpt_wait_cmd_size(void) +u32 gv11b_fifo_get_syncpt_wait_cmd_size(void) { return 8; } -static void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, +void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, bool wfi_cmd, struct priv_cmd_entry *cmd, u32 id, u64 gpu_va_base) { @@ -1706,13 +1706,13 @@ static void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, nvgpu_mem_wr32(g, cmd->mem, off++, 0); } -static u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd) +u32 gv11b_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd) { return 9; } #endif /* CONFIG_TEGRA_GK20A_NVHOST */ -static int gv11b_init_fifo_setup_hw(struct gk20a *g) +int gv11b_init_fifo_setup_hw(struct gk20a *g) { struct fifo_gk20a *f = &g->fifo; @@ -1790,58 +1790,3 @@ void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g, else *pbdma_id = FIFO_INVAL_PBDMA_ID; } - -void gv11b_init_fifo(struct gpu_ops *gops) -{ - gp10b_init_fifo(gops); - /* for gv11b no need to do any thing special for fifo hw setup */ - gops->fifo.init_fifo_setup_hw = gv11b_init_fifo_setup_hw; - gops->fifo.runlist_entry_size = ram_rl_entry_size_v; - gops->fifo.get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry; - gops->fifo.get_ch_runlist_entry = gv11b_get_ch_runlist_entry; - gops->fifo.get_num_fifos = gv11b_fifo_get_num_fifos; - gops->fifo.userd_gp_get = gv11b_userd_gp_get; - gops->fifo.userd_gp_put = gv11b_userd_gp_put; - gops->fifo.userd_pb_get = gv11b_userd_pb_get; - gops->fifo.setup_ramfc = channel_gv11b_setup_ramfc; - gops->fifo.resetup_ramfc = NULL; - gops->fifo.unbind_channel = channel_gv11b_unbind; - gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; - gops->fifo.free_channel_ctx_header = gv11b_free_subctx_header; - gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v; - gops->fifo.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc; - gops->fifo.trigger_mmu_fault = NULL; - gops->fifo.get_mmu_fault_info = NULL; - gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status; - gops->fifo.dump_eng_status = gv11b_dump_eng_status; - gops->fifo.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc; - gops->fifo.intr_0_error_mask = gv11b_fifo_intr_0_error_mask; - gops->fifo.preempt_channel = gv11b_fifo_preempt_channel; - gops->fifo.preempt_tsg = gv11b_fifo_preempt_tsg; - gops->fifo.is_preempt_pending = gv11b_fifo_is_preempt_pending; - gops->fifo.preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg; - gops->fifo.init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs; - gops->fifo.reset_enable_hw = gv11b_init_fifo_reset_enable_hw; - gops->fifo.teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg; - gops->fifo.handle_sched_error = gv11b_fifo_handle_sched_error; - gops->fifo.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout; - gops->fifo.handle_pbdma_intr_0 = - gv11b_fifo_handle_pbdma_intr_0; - gops->fifo.handle_pbdma_intr_1 = - gv11b_fifo_handle_pbdma_intr_1; - gops->fifo.init_eng_method_buffers = - gv11b_fifo_init_eng_method_buffers; - gops->fifo.deinit_eng_method_buffers = - gv11b_fifo_deinit_eng_method_buffers; -#ifdef CONFIG_TEGRA_GK20A_NVHOST - gops->fifo.alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf; - gops->fifo.free_syncpt_buf = gv11b_fifo_free_syncpt_buf; - gops->fifo.add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd; - gops->fifo.get_syncpt_wait_cmd_size = - gv11b_fifo_get_syncpt_wait_cmd_size; - gops->fifo.add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd; - gops->fifo.get_syncpt_incr_cmd_size = - gv11b_fifo_get_syncpt_incr_cmd_size; -#endif - -} -- cgit v1.2.2 From 3197a918d5052c71ad854f6b22fdb35bfe7cebe2 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Thu, 10 Aug 2017 16:34:16 -0700 Subject: gpu: nvgpu: gv11b: add max_subctx_count to g->fifo.t19x - For better performance. It used to read register every time referencing max_subctx_count. - Avoid reading registers for vgpu. Jira VFND-3797 Change-Id: Id6e6b15a0d9a035795e8a9a2c6bb63524c5eb544 Signed-off-by: Richard Zhao Reviewed-on: https://git-master.nvidia.com/r/1537009 Reviewed-by: svccoveritychecker Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index e210d40d..bd769f75 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -40,6 +40,7 @@ #include #include #include +#include #include "fifo_gv11b.h" #include "subctx_gv11b.h" @@ -1717,16 +1718,20 @@ int gv11b_init_fifo_setup_hw(struct gk20a *g) struct fifo_gk20a *f = &g->fifo; f->t19x.usermode_regs = g->regs + usermode_cfg0_r(); + f->t19x.max_subctx_count = + gr_pri_fe_chip_def_info_max_veid_count_v( + gk20a_readl(g, gr_pri_fe_chip_def_info_r())); return 0; } static u32 gv11b_mmu_fault_id_to_gr_veid(struct gk20a *g, u32 gr_eng_fault_id, u32 mmu_fault_id) { + struct fifo_gk20a *f = &g->fifo; u32 num_subctx; u32 veid = FIFO_INVAL_VEID; - num_subctx = gv11b_get_max_subctx_count(g); + num_subctx = f->t19x.max_subctx_count; if (mmu_fault_id >= gr_eng_fault_id && mmu_fault_id < (gr_eng_fault_id + num_subctx)) -- cgit v1.2.2 From 6ff92bfb6e1ed68e29cef279f3275ac75ceaa4db Mon Sep 17 00:00:00 2001 From: Debarshi Dutta Date: Sun, 6 Aug 2017 14:44:11 +0530 Subject: gpu: nvgpu: Add wrapper over atomic_t and atomic64_t - added wrapper structs nvgpu_atomic_t and nvgpu_atomic64_t over atomic_t and atomic64_t - added nvgpu_atomic_* and nvgpu_atomic64_* APIs to access the above wrappers. JIRA NVGPU-121 Change-Id: I61667bb0a84c2fc475365abb79bffb42b8b4786a Signed-off-by: Debarshi Dutta Reviewed-on: https://git-master.nvidia.com/r/1533641 Reviewed-by: Terje Bergstrom Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity Tested-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index bd769f75..c2792414 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -315,11 +315,10 @@ void gv11b_dump_channel_status_ramfc(struct gk20a *g, inst_mem[ram_fc_sem_payload_lo_w()], inst_mem[ram_fc_sem_execute_w()]); if (hw_sema) - gk20a_debug_output(o, "SEMA STATE: value: 0x%08x " - "next_val: 0x%08x addr: 0x%010llx\n", - __nvgpu_semaphore_read(hw_sema), - atomic_read(&hw_sema->next_value), - nvgpu_hw_sema_addr(hw_sema)); + gk20a_debug_output(o, "SEMA STATE: value: 0x%08x next_val: 0x%08x addr: 0x%010llx\n", + __nvgpu_semaphore_read(hw_sema), + nvgpu_atomic_read(&hw_sema->next_value), + nvgpu_hw_sema_addr(hw_sema)); gk20a_debug_output(o, "\n"); } -- cgit v1.2.2 From ddeadd8cf250efa190ebc349776e90420a302038 Mon Sep 17 00:00:00 2001 From: Debarshi Dutta Date: Fri, 18 Aug 2017 16:29:55 +0530 Subject: gpu: nvgpu: Nvgpu abstraction for linux barriers. construct wrapper nvgpu_* methods to replace mb,rmb,wmb,smp_mb,smp_rmb,smp_wmb,read_barrier_depends and smp_read_barrier_depends. NVGPU-122 Change-Id: I97380c3b211733e682f198c35f35640af203359c Signed-off-by: Debarshi Dutta Reviewed-on: https://git-master.nvidia.com/r/1541197 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity Reviewed-by: Sourab Gupta GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index c2792414..48d14e74 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -247,7 +248,7 @@ void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) nvgpu_mem_wr32(g, userd_mem, offset + ram_userd_gp_put_w(), c->gpfifo.put); /* commit everything to cpu */ - smp_mb(); + nvgpu_smp_mb(); gv11b_ring_channel_doorbell(c); } -- cgit v1.2.2 From 5df1d3ff7a23ec39ea5fc841b2dbfe98fa74b44a Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Fri, 18 Aug 2017 15:27:20 -0700 Subject: gpu: nvgpu: gv11b: release eng_method_buffers In case of any error while allocating eng_method_buffers release allocated buffers gracefully. Change-Id: Ic9d86b63d2405fd0113e63f2fc3f96166a4de9b5 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1541510 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 48d14e74..80bb64a0 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1543,7 +1543,8 @@ void gv11b_fifo_init_eng_method_buffers(struct gk20a *g, { struct vm_gk20a *vm = g->mm.bar2.vm; int err = 0; - unsigned int i, runque, method_buffer_size; + int i; + unsigned int runque, method_buffer_size; unsigned int num_pbdma = g->fifo.num_pbdma; if (tsg->eng_method_buffers != NULL) @@ -1565,9 +1566,9 @@ void gv11b_fifo_init_eng_method_buffers(struct gk20a *g, break; } if (err) { - for (i = runque; i < runque; i--) + for (i = (runque - 1); i >= 0; i--) nvgpu_dma_unmap_free(vm, - &tsg->eng_method_buffers[runque]); + &tsg->eng_method_buffers[i]); nvgpu_kfree(g, tsg->eng_method_buffers); tsg->eng_method_buffers = NULL; -- cgit v1.2.2 From 52f50addc6cedf57fc3d8ff06314921499fb59e3 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 13 Sep 2017 17:35:03 +0530 Subject: gpu: nvgpu: add TSG enable/disable operations Add TSG enable/disable operations for gv11b/gv100 To disable a TSG we continue to use gk20a_disable_tsg() To enable a TSG add new API gv11b_fifo_enable_tsg() since TSG enable sequence is different for Volta than previous versions For Volta it is sufficient to loop over all the channels in TSG and enable them sequentially Bug 1739362 Change-Id: Id4b4684959204c6101ceda83487a41fbfcba8b5f Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1560642 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 80bb64a0..1d5e593c 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -785,6 +785,21 @@ static int __locked_fifo_preempt_runlists(struct gk20a *g, u32 runlists_mask) return ret; } +/* TSG enable sequence applicable for Volta and onwards */ +int gv11b_fifo_enable_tsg(struct tsg_gk20a *tsg) +{ + struct gk20a *g = tsg->g; + struct channel_gk20a *ch; + + down_read(&tsg->ch_list_lock); + nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) { + g->ops.fifo.enable_channel(ch); + } + up_read(&tsg->ch_list_lock); + + return 0; +} + int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) { struct fifo_gk20a *f = &g->fifo; -- cgit v1.2.2 From f720b309f1ea87a301bcb216983396f3d9c55abc Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 14 Sep 2017 05:48:07 -0700 Subject: gpu: nvgpu: add tsg_verify_status_faulted operation Add new API gv11b_fifo_tsg_verify_status_faulted() and use that as g->ops.fifo.tsg_verify_status_faulted operation for gv11b/gv100 This API will check if channel has ENG_FAULTED status set, if yes it will clear CE method buffer in case saved out channel is same as faulted channel We need to write 0 to method count to invalidate CE method buffer Also set g->ops.fifo.tsg_verify_status_ctx_reload operation for gv11b/gv100 Bug 200327095 Change-Id: I9d2b0f13faf881b30680219bbcadfd4969c4dff6 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1560643 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 1d5e593c..b4e4b875 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1811,3 +1811,38 @@ void gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid(struct gk20a *g, else *pbdma_id = FIFO_INVAL_PBDMA_ID; } + +static bool gk20a_fifo_channel_status_is_eng_faulted(struct gk20a *g, u32 chid) +{ + u32 channel = gk20a_readl(g, ccsr_channel_r(chid)); + + return ccsr_channel_eng_faulted_v(channel) == + ccsr_channel_eng_faulted_true_v(); +} + +void gv11b_fifo_tsg_verify_status_faulted(struct channel_gk20a *ch) +{ + struct gk20a *g = ch->g; + struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; + + /* + * If channel has FAULTED set, clear the CE method buffer + * if saved out channel is same as faulted channel + */ + if (!gk20a_fifo_channel_status_is_eng_faulted(g, ch->chid)) + return; + + if (tsg->eng_method_buffers == NULL) + return; + + /* + * CE method buffer format : + * DWord0 = method count + * DWord1 = channel id + * + * It is sufficient to write 0 to method count to invalidate + */ + if ((u32)ch->chid == + nvgpu_mem_rd32(g, &tsg->eng_method_buffers[ASYNC_CE_RUNQUE], 1)) + nvgpu_mem_wr32(g, &tsg->eng_method_buffers[ASYNC_CE_RUNQUE], 0, 0); +} -- cgit v1.2.2 From 31a50f07e4458b43f46a9612e4b27893a50d53b3 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 31 Aug 2017 11:15:50 -0700 Subject: gpu: nvgpu: gv11b: Set pbdma, fb and ctxsw timeout for pre-si fb and ctxsw timeout detection should be disabled for simulation architectures. Also set timeouts to max for pbdma, fb and ctxsw timeouts. Bug 200289427 Change-Id: I8723d5ee9ea2535f401b1972c8c14ffab8f9504a Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1549522 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 43 +++++++++++++++++++++++++++++++----- 1 file changed, 37 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b4e4b875..6f9e44fb 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1166,10 +1166,27 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) timeout = gk20a_readl(g, fifo_fb_timeout_r()); nvgpu_log_info(g, "fifo_fb_timeout reg val = 0x%08x", timeout); + if (!nvgpu_platform_is_silicon(g)) { + timeout = set_field(timeout, fifo_fb_timeout_period_m(), + fifo_fb_timeout_period_max_f()); + timeout = set_field(timeout, fifo_fb_timeout_detection_m(), + fifo_fb_timeout_detection_disabled_f()); + nvgpu_log_info(g, "new fifo_fb_timeout reg val = 0x%08x", + timeout); + gk20a_writel(g, fifo_fb_timeout_r(), timeout); + } + for (i = 0; i < host_num_pbdma; i++) { timeout = gk20a_readl(g, pbdma_timeout_r(i)); nvgpu_log_info(g, "pbdma_timeout reg val = 0x%08x", timeout); + if (!nvgpu_platform_is_silicon(g)) { + timeout = set_field(timeout, pbdma_timeout_period_m(), + pbdma_timeout_period_max_f()); + nvgpu_log_info(g, "new pbdma_timeout reg val = 0x%08x", + timeout); + gk20a_writel(g, pbdma_timeout_r(i), timeout); + } } /* clear and enable pbdma interrupt */ @@ -1189,12 +1206,26 @@ int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) /* clear ctxsw timeout interrupts */ gk20a_writel(g, fifo_intr_ctxsw_timeout_r(), ~0); - /* enable ctxsw timeout */ - timeout = GRFIFO_TIMEOUT_CHECK_PERIOD_US; - timeout = scale_ptimer(timeout, - ptimer_scalingfactor10x(g->ptimer_src_freq)); - timeout |= fifo_eng_ctxsw_timeout_detection_enabled_f(); - gk20a_writel(g, fifo_eng_ctxsw_timeout_r(), timeout); + if (nvgpu_platform_is_silicon(g)) { + /* enable ctxsw timeout */ + timeout = GRFIFO_TIMEOUT_CHECK_PERIOD_US; + timeout = scale_ptimer(timeout, + ptimer_scalingfactor10x(g->ptimer_src_freq)); + timeout |= fifo_eng_ctxsw_timeout_detection_enabled_f(); + gk20a_writel(g, fifo_eng_ctxsw_timeout_r(), timeout); + } else { + timeout = gk20a_readl(g, fifo_eng_ctxsw_timeout_r()); + nvgpu_log_info(g, "fifo_eng_ctxsw_timeout reg val = 0x%08x", + timeout); + timeout = set_field(timeout, fifo_eng_ctxsw_timeout_period_m(), + fifo_eng_ctxsw_timeout_period_max_f()); + timeout = set_field(timeout, + fifo_eng_ctxsw_timeout_detection_m(), + fifo_eng_ctxsw_timeout_detection_disabled_f()); + nvgpu_log_info(g, "new fifo_eng_ctxsw_timeout reg val = 0x%08x", + timeout); + gk20a_writel(g, fifo_eng_ctxsw_timeout_r(), timeout); + } /* clear runlist interrupts */ gk20a_writel(g, fifo_intr_runlist_r(), ~0); -- cgit v1.2.2 From 622072d1c069581da80b14a7ea64e20d283877ab Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 11 Sep 2017 10:33:51 -0700 Subject: gpu: nvgpu: gv11b: poll tsgid for preempt done Use tsgid for polling preemption completion since id and next_id in pbdma and eng status point to tsgid Bug 200277163 Bug 1958308 Change-Id: I5636ce1f8b21ddac4c93d92ce0527fe0307f2cfc Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1557253 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 6f9e44fb..dce8ce9b 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -710,20 +710,24 @@ int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, u32 runlist_id; int func_ret; int ret = 0; + u32 tsgid; - gk20a_dbg_fn(""); - - if (id_type == ID_TYPE_TSG) + if (id_type == ID_TYPE_TSG) { runlist_id = f->tsg[id].runlist_id; - else + tsgid = id; + } else { runlist_id = f->channel[id].runlist_id; + tsgid = f->channel[id].tsgid; + } + + nvgpu_log_info(g, "Check preempt pending for tsgid = %u", tsgid); runlist_served_pbdmas = f->runlist_info[runlist_id].pbdma_bitmask; runlist_served_engines = f->runlist_info[runlist_id].eng_bitmask; for_each_set_bit(pbdma_id, &runlist_served_pbdmas, f->num_pbdma) { - func_ret = gv11b_fifo_poll_pbdma_chan_status(g, id, pbdma_id, + func_ret = gv11b_fifo_poll_pbdma_chan_status(g, tsgid, pbdma_id, timeout_rc_type); if (func_ret != 0) { gk20a_dbg_info("preempt timeout pbdma %d", pbdma_id); @@ -735,7 +739,7 @@ int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, for_each_set_bit(act_eng_id, &runlist_served_engines, f->num_engines) { - func_ret = gv11b_fifo_poll_eng_ctx_status(g, id, act_eng_id, + func_ret = gv11b_fifo_poll_eng_ctx_status(g, tsgid, act_eng_id, &f->runlist_info[runlist_id].reset_eng_bitmask, timeout_rc_type); -- cgit v1.2.2 From ca2560af809a12d7aabd349b2b8e73932e70ffba Mon Sep 17 00:00:00 2001 From: Sreejith V Date: Mon, 18 Sep 2017 18:42:46 +0530 Subject: gpu: nvgpu: gv11b: remove misleading intendation warning Bug 200348860 Bug 200291879 Change-Id: Ia1e651d8365eae6e7aef69d79923d644c7067211 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1563869 Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index dce8ce9b..189fe3f0 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -977,9 +977,9 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, client_type = mmfault->client_type; if (gk20a_is_channel_marked_as_tsg(refch)) tsg = &g->fifo.tsg[refch->tsgid]; - gv11b_fifo_reset_pbdma_and_eng_faulted(g, refch, - mmfault->faulted_pbdma, - mmfault->faulted_engine); + gv11b_fifo_reset_pbdma_and_eng_faulted(g, refch, + mmfault->faulted_pbdma, + mmfault->faulted_engine); } else { if (id_type == ID_TYPE_TSG) tsg = &g->fifo.tsg[id]; -- cgit v1.2.2 From d61643c0200983dc340d37962bb0a3ca900a3e97 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 25 Sep 2017 08:59:28 -0700 Subject: gpu: nvgpu: gv11b: Change license for common files to MIT Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity Reviewed-by: David Martinez Nieto Reviewed-by: Seshendra Gadagottu Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 189fe3f0..8c9e58f7 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -3,14 +3,23 @@ * * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include #include -- cgit v1.2.2 From 1f6755b287cd5382a6e16baf0342bf6a7ab97f6c Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 26 Sep 2017 11:22:01 -0700 Subject: gpu: nvgpu: gv11b: set correct max subctx count Reading gr_pri_fe_chip_def_info_r() during gv11b_init_fifo_setup_hw on RTL platforms is giving "0xbadf1201" error because fecs part of priv ring is still in reset. This needs to be fixed after identifying relevant engine that needs to be brought out of reset. Until that time, use constant value from hw definition(whose value is 64): gr_pri_fe_chip_def_info_max_veid_count_init_v(). Bug 1983643 Change-Id: I66f2b6491c9d444c6f6919e76c72ec33a904bc90 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1568139 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Tested-by: Seema Khowala GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 8c9e58f7..26e444cc 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1779,8 +1779,7 @@ int gv11b_init_fifo_setup_hw(struct gk20a *g) f->t19x.usermode_regs = g->regs + usermode_cfg0_r(); f->t19x.max_subctx_count = - gr_pri_fe_chip_def_info_max_veid_count_v( - gk20a_readl(g, gr_pri_fe_chip_def_info_r())); + gr_pri_fe_chip_def_info_max_veid_count_init_v(); return 0; } -- cgit v1.2.2 From 0d63e22a9920eb1e3d8653665cda650eca2311cd Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 27 Sep 2017 11:18:13 -0700 Subject: gpu: nvgpu: gv11b: check for memory aperture type Check for memory aperture type before setting relevant sysmem non-coherent or vidmem flags in ram entry. Modified following functions to correct memory aperture type: gv11b_get_ch_runlist_entry gv11b_subctx_commit_pdb Added following hw constants for chan_inst_target: ram_rl_entry_chan_inst_target_sys_mem_coh_v ram_rl_entry_chan_inst_target_vid_mem_v Change-Id: I85698044b9fe4c8baed71121845e4fb69dc33922 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1569521 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 26e444cc..5fe40663 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -107,9 +107,13 @@ void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) ram_rl_entry_chan_runqueue_selector_f( c->t19x.runqueue_sel) | ram_rl_entry_chan_userd_target_f( - ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()) | + nvgpu_aperture_mask(g, &g->fifo.userd, + ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(), + ram_rl_entry_chan_userd_target_vid_mem_v())) | ram_rl_entry_chan_inst_target_f( - ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()); + nvgpu_aperture_mask(g, &c->inst_block, + ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(), + ram_rl_entry_chan_inst_target_vid_mem_v())); addr_lo = u64_lo32(c->userd_iova) >> ram_rl_entry_chan_userd_ptr_align_shift_v(); -- cgit v1.2.2 From 506f891f76800b059e960a195bb0da4c71cb2e16 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 5 Jul 2017 22:55:39 -0700 Subject: gpu: nvgpu: gv11b: add syncpt shim ro map For sync-point read map, create read only map per vm and share with all channels that are using same vm. Now restrict rw map to single syncpoint shim memory range. JIRA GPUT19X-2 Change-Id: Ibd0b82d1cdb8861e1dbb073b27da1f9c9ab1d2ab Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1514339 Reviewed-by: svc-mobile-coverity Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 48 ++++++++++++++++++++---------------- 1 file changed, 27 insertions(+), 21 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 5fe40663..b8798033 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1664,33 +1664,41 @@ void gv11b_fifo_deinit_eng_method_buffers(struct gk20a *g, int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, u32 syncpt_id, struct nvgpu_mem *syncpt_buf) { - struct page **pages; u32 nr_pages; - u32 i; int err = 0; struct gk20a *g = c->g; + struct vm_gk20a *vm = c->vm; /* - * Add rw mapping for entire syncpt shim for current channel vm - * TODO : This needs to replaced with a new mecahnism where - * only current syncpoint range will be rw and other sync - * points range is read only for current channel vm. Also share - * these mapping accross channels if they share same vm - */ - nr_pages = DIV_ROUND_UP(g->syncpt_unit_size, PAGE_SIZE); - pages = nvgpu_kzalloc(g, sizeof(struct page *) * nr_pages); - for (i = 0; i < nr_pages; i++) - pages[i] = phys_to_page(g->syncpt_unit_base + - PAGE_SIZE * i); - __nvgpu_mem_create_from_pages(g, syncpt_buf, pages, nr_pages); - nvgpu_kfree(g, pages); + * Add ro map for complete sync point shim range in vm + * All channels sharing same vm will share same ro mapping. + * Create rw map for current channel sync point + */ + if (!vm->syncpt_ro_map_gpu_va) { + vm->syncpt_ro_map_gpu_va = nvgpu_gmmu_map(c->vm, + &g->syncpt_mem, g->syncpt_unit_size, + 0, gk20a_mem_flag_read_only, + false, APERTURE_SYSMEM); + + if (!vm->syncpt_ro_map_gpu_va) { + nvgpu_err(g, "failed to ro map syncpt buffer"); + nvgpu_dma_free(g, &g->syncpt_mem); + err = -ENOMEM; + } + } + + nr_pages = DIV_ROUND_UP(g->syncpt_size, PAGE_SIZE); + __nvgpu_mem_create_from_phys(g, syncpt_buf, + (g->syncpt_unit_base + + nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id)), + nr_pages); syncpt_buf->gpu_va = nvgpu_gmmu_map(c->vm, syncpt_buf, - g->syncpt_unit_size, 0, gk20a_mem_flag_none, + g->syncpt_size, 0, gk20a_mem_flag_none, false, APERTURE_SYSMEM); if (!syncpt_buf->gpu_va) { - nvgpu_err(c->g, "failed to map syncpt buffer"); - nvgpu_dma_free(c->g, syncpt_buf); + nvgpu_err(g, "failed to map syncpt buffer"); + nvgpu_dma_free(g, syncpt_buf); err = -ENOMEM; } return err; @@ -1740,11 +1748,9 @@ u32 gv11b_fifo_get_syncpt_wait_cmd_size(void) void gv11b_fifo_add_syncpt_incr_cmd(struct gk20a *g, bool wfi_cmd, struct priv_cmd_entry *cmd, - u32 id, u64 gpu_va_base) + u32 id, u64 gpu_va) { u32 off = cmd->off; - u64 gpu_va = gpu_va_base + - nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(id); gk20a_dbg_fn(""); -- cgit v1.2.2 From b0092ea95c6e1f695912cdb0b13767f3881cb22f Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 27 Sep 2017 15:05:50 -0700 Subject: gpu: nvgpu: gv11b: Abstract IO aperture accessors Implement T19x specific usermode aperture initialization functions. Move usermode_regs field to nvgpu_os_linux_t19x, because it is Linux specific. JIRA NVGPU-259 Change-Id: I9d6ce243a692ab48209d468288ed85f89fb26770 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1569699 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b8798033..e9830c0e 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -61,15 +61,6 @@ static void gv11b_fifo_init_ramfc_eng_method_buffer(struct gk20a *g, struct channel_gk20a *ch, struct nvgpu_mem *mem); -static inline void gv11b_usermode_writel(struct gk20a *g, u32 r, u32 v) -{ - struct fifo_gk20a *f = &g->fifo; - void __iomem *reg = f->t19x.usermode_regs + (r - usermode_cfg0_r()); - - writel_relaxed(v, reg); - gk20a_dbg(gpu_dbg_reg, "usermode r=0x%x v=0x%x", r, v); -} - void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) { @@ -1787,7 +1778,6 @@ int gv11b_init_fifo_setup_hw(struct gk20a *g) { struct fifo_gk20a *f = &g->fifo; - f->t19x.usermode_regs = g->regs + usermode_cfg0_r(); f->t19x.max_subctx_count = gr_pri_fe_chip_def_info_max_veid_count_init_v(); return 0; -- cgit v1.2.2 From 3fc7c5f75ef4a6399e060d8cbfd4d7dc40c82588 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 16 Oct 2017 14:56:22 -0700 Subject: gpu: nvgpu: gv11b: Use nvgpu_rwsem as TSG channel lock Use abstract nvgpu_rwsem as TSG channel list lock instead of the Linux specific rw_semaphore. JIRA NVGPU-259 Change-Id: I5f6c918464315e3d140bea0c61a619c3712619c1 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1579934 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index e9830c0e..7bb3d654 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -545,11 +545,11 @@ static void gv11b_reset_eng_faulted_tsg(struct tsg_gk20a *tsg) struct gk20a *g = tsg->g; struct channel_gk20a *ch; - down_read(&tsg->ch_list_lock); + nvgpu_rwsem_down_read(&tsg->ch_list_lock); list_for_each_entry(ch, &tsg->ch_list, ch_entry) { gv11b_reset_eng_faulted_ch(g, ch->chid); } - up_read(&tsg->ch_list_lock); + nvgpu_rwsem_up_read(&tsg->ch_list_lock); } static void gv11b_reset_pbdma_faulted_ch(struct gk20a *g, u32 chid) @@ -566,11 +566,11 @@ static void gv11b_reset_pbdma_faulted_tsg(struct tsg_gk20a *tsg) struct gk20a *g = tsg->g; struct channel_gk20a *ch; - down_read(&tsg->ch_list_lock); + nvgpu_rwsem_down_read(&tsg->ch_list_lock); list_for_each_entry(ch, &tsg->ch_list, ch_entry) { gv11b_reset_pbdma_faulted_ch(g, ch->chid); } - up_read(&tsg->ch_list_lock); + nvgpu_rwsem_up_read(&tsg->ch_list_lock); } void gv11b_fifo_reset_pbdma_and_eng_faulted(struct gk20a *g, @@ -799,11 +799,11 @@ int gv11b_fifo_enable_tsg(struct tsg_gk20a *tsg) struct gk20a *g = tsg->g; struct channel_gk20a *ch; - down_read(&tsg->ch_list_lock); + nvgpu_rwsem_down_read(&tsg->ch_list_lock); nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) { g->ops.fifo.enable_channel(ch); } - up_read(&tsg->ch_list_lock); + nvgpu_rwsem_up_read(&tsg->ch_list_lock); return 0; } -- cgit v1.2.2 From 6114553413297dbcae637bc50ef2ff2a6c0858d1 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 19 Oct 2017 10:12:24 -0700 Subject: gpu: nvgpu: gv100: fix timeout handling GV100 has a larger vidmem size and a slower sideband to sysmem so timeouts need to be adjusted to avoid false positives. JIRA: NVGPUGV100-36 Change-Id: I3cbc19aa1158c89bc48ae1fa6ec4bc755cd9389d Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1582092 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 7bb3d654..4a03e6d9 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -372,6 +372,11 @@ u32 gv11b_fifo_intr_0_error_mask(struct gk20a *g) return intr_0_error_mask; } +u32 gv11b_fifo_get_preempt_timeout(struct gk20a *g) +{ + return gk20a_get_gr_idle_timeout(g); +} + static int gv11b_fifo_poll_pbdma_chan_status(struct gk20a *g, u32 id, u32 pbdma_id, unsigned int timeout_rc_type) { @@ -405,7 +410,7 @@ static int gv11b_fifo_poll_pbdma_chan_status(struct gk20a *g, u32 id, gk20a_writel(g, pbdma_intr_1_r(pbdma_id), pbdma_intr_1); } - nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), + nvgpu_timeout_init(g, &timeout, g->ops.fifo.get_preempt_timeout(g), NVGPU_TIMER_CPU_TIMER); /* Verify that ch/tsg is no longer on the pbdma */ @@ -465,7 +470,7 @@ static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, u32 ctx_stat; int ret = -EBUSY; - nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), + nvgpu_timeout_init(g, &timeout, g->ops.fifo.get_preempt_timeout(g), NVGPU_TIMER_CPU_TIMER); /* Check if ch/tsg has saved off the engine or if ctxsw is hung */ @@ -686,7 +691,7 @@ static int gv11b_fifo_poll_runlist_preempt_pending(struct gk20a *g, u32 delay = GR_IDLE_CHECK_DEFAULT; int ret = -EBUSY; - nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), + nvgpu_timeout_init(g, &timeout, g->ops.fifo.get_preempt_timeout(g), NVGPU_TIMER_CPU_TIMER); do { if (!((gk20a_readl(g, fifo_runlist_preempt_r())) & -- cgit v1.2.2 From 0899e11d4bb630381607a0c245f72476e2e9209e Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Fri, 6 Oct 2017 17:20:12 -0700 Subject: gpu: nvgpu: Cleanup generic MM code t19x changes necessary for change in core MM code. JIRA NVGPU-30 Change-Id: I62f419450c1a33d0826390d7cbb5ad93569f8c89 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1577265 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 4a03e6d9..dc3b641a 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -34,6 +34,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -112,9 +113,9 @@ void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) runlist[0] = runlist_entry | ram_rl_entry_chan_userd_ptr_lo_f(addr_lo); runlist[1] = ram_rl_entry_chan_userd_ptr_hi_f(addr_hi); - addr_lo = u64_lo32(gk20a_mm_inst_block_addr(g, &c->inst_block)) >> + addr_lo = u64_lo32(nvgpu_inst_block_addr(g, &c->inst_block)) >> ram_rl_entry_chan_inst_ptr_align_shift_v(); - addr_hi = u64_hi32(gk20a_mm_inst_block_addr(g, &c->inst_block)); + addr_hi = u64_hi32(nvgpu_inst_block_addr(g, &c->inst_block)); runlist[2] = ram_rl_entry_chan_inst_ptr_lo_f(addr_lo) | ram_rl_entry_chid_f(c->chid); -- cgit v1.2.2 From afd1649cfcae97e873663586d55f9a4cfd671808 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 26 Oct 2017 15:20:39 -0700 Subject: gpu: nvgpu: Move ctxsw_trace_gk20a.c to common/linux Fixups for the change of name subject in nvgpu. JIRA NVGPU-287 Change-Id: I6c19733079061a42786b94fc48db374d715ccbef Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1586548 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index dc3b641a..d74ddacd 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -1075,10 +1075,12 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, } } +#ifdef CONFIG_GK20A_CTXSW_TRACE if (refch) gk20a_ctxsw_trace_channel_reset(g, refch); else if (tsg) gk20a_ctxsw_trace_tsg_reset(g, tsg); +#endif gk20a_fifo_set_runlist_state(g, runlists_mask, RUNLIST_ENABLED, !RUNLIST_INFO_MUTEX_LOCKED); -- cgit v1.2.2 From f472922b3582dbba78b633958a4cb7b65ddb3f03 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Tue, 31 Oct 2017 12:23:30 -0700 Subject: gpu: nvgpu: Split ctxsw_trace API into non-Linux component T19x component for similar change in the main nvgpu code. JIRA NVGPU-287 Change-Id: Ib126b3d1fb562850fbb3ab89103f2a7fdaa13306 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1589430 Reviewed-by: Terje Bergstrom Reviewed-by: svc-mobile-coverity Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index d74ddacd..4c3b1186 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -35,10 +35,10 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" -#include "gk20a/ctxsw_trace_gk20a.h" #include "gk20a/channel_gk20a.h" #include "gp10b/fifo_gp10b.h" -- cgit v1.2.2 From d99b72974d06d4b3bc577bae8dc721b7b8f3cde9 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 8 Nov 2017 15:59:31 -0800 Subject: gpu: nvgpu: gv11b: clear channel status After unbinding channel, following fields in channel status needs to be cleared manually: ccsr_channel_enable_clr_true ccsr_channel_pbdma_faulted_reset ccsr_channel_eng_faulted_reset Unbinding channel expected to clear all other channel status fields. Bug 1972365 Change-Id: Ibfd84df2f41adc2eb437a026acde3f3d618d7758 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1594671 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 4c3b1186..a3cb9292 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -260,9 +260,20 @@ void gv11b_userd_gp_put(struct gk20a *g, struct channel_gk20a *c) void channel_gv11b_unbind(struct channel_gk20a *ch) { + struct gk20a *g = ch->g; + gk20a_dbg_fn(""); - gk20a_fifo_channel_unbind(ch); + if (nvgpu_atomic_cmpxchg(&ch->bound, true, false)) { + gk20a_writel(g, ccsr_channel_inst_r(ch->chid), + ccsr_channel_inst_ptr_f(0) | + ccsr_channel_inst_bind_false_f()); + + gk20a_writel(g, ccsr_channel_r(ch->chid), + ccsr_channel_enable_clr_true_f() | + ccsr_channel_pbdma_faulted_reset_f() | + ccsr_channel_eng_faulted_reset_f()); + } } u32 gv11b_fifo_get_num_fifos(struct gk20a *g) -- cgit v1.2.2 From 72b51a129fda4a89f226aad7c99f062977a07189 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 22 Sep 2017 15:07:13 -0700 Subject: gpu: nvgpu: gv11b: detect stall intr during preemption Check for interrupts or hangs while waiting for the preempt to complete. During pbdma/eng preempt done polling, any stalling interrupts relating to the runlist must be detected and handled in order for the preemption to complete. When PBDMA fault or CE fault occurs, the PBDMA will save out automatically. TSG related to the context in which the fault occurred will not be scheduled again until the fault is handled. In the case of some other issue requiring the engine to be reset, TSG will need to be manually preempted. In all cases, a PBDMA interrupt may occur prior to the PBDMA being able to switch out. SW must handle these interrupts according to the relevant handling procedure before the PBDMA preempt can complete. Opt for eng reset instead of waiting for preemption to be finished when there is any stall interrupt pending during engine context preempt completion. Bug 200277163 Bug 1945121 Change-Id: Icaef79e3046d82987b8486d15cbfc8365aa26f2e Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1522914 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: David Martinez Nieto Tested-by: David Martinez Nieto Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 89 +++++++++++++++++------------------- 1 file changed, 43 insertions(+), 46 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index a3cb9292..f87c6dea 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -56,6 +56,7 @@ #include "fifo_gv11b.h" #include "subctx_gv11b.h" #include "gr_gv11b.h" +#include "mc_gv11b.h" #define PBDMA_SUBDEVICE_ID 1 @@ -393,45 +394,35 @@ static int gv11b_fifo_poll_pbdma_chan_status(struct gk20a *g, u32 id, u32 pbdma_id, unsigned int timeout_rc_type) { struct nvgpu_timeout timeout; - unsigned long delay = GR_IDLE_CHECK_DEFAULT; + unsigned long delay = GR_IDLE_CHECK_DEFAULT; /* in micro seconds */ u32 pbdma_stat; u32 chan_stat; int ret = -EBUSY; - /* - * If the PBDMA has a stalling interrupt and receives a NACK, the PBDMA - * won't save out until the STALLING interrupt is cleared. Note that - * the stalling interrupt need not be directly addressed, as simply - * clearing of the interrupt bit will be sufficient to allow the PBDMA - * to save out. If the stalling interrupt was due to a SW method or - * another deterministic failure, the PBDMA will assert it when the - * channel is reloaded/resumed. Note that the fault will still be - * reported to SW. - */ - - if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { - /* called from recovery */ - u32 pbdma_intr_0, pbdma_intr_1; - - pbdma_intr_0 = gk20a_readl(g, pbdma_intr_0_r(pbdma_id)); - pbdma_intr_1 = gk20a_readl(g, pbdma_intr_1_r(pbdma_id)); - - if (pbdma_intr_0) - gk20a_writel(g, pbdma_intr_0_r(pbdma_id), pbdma_intr_0); - if (pbdma_intr_1) - gk20a_writel(g, pbdma_intr_1_r(pbdma_id), pbdma_intr_1); - } - + /* timeout in milli seconds */ nvgpu_timeout_init(g, &timeout, g->ops.fifo.get_preempt_timeout(g), NVGPU_TIMER_CPU_TIMER); + nvgpu_log(g, gpu_dbg_info, "wait preempt pbdma %d", pbdma_id); /* Verify that ch/tsg is no longer on the pbdma */ do { + /* + * If the PBDMA has a stalling interrupt and receives a NACK, + * the PBDMA won't save out until the STALLING interrupt is + * cleared. Stalling interrupt need not be directly addressed, + * as simply clearing of the interrupt bit will be sufficient + * to allow the PBDMA to save out. If the stalling interrupt + * was due to a SW method or another deterministic failure, + * the PBDMA will assert it when the channel is reloaded + * or resumed. Note that the fault will still be + * reported to SW. + */ + + gk20a_fifo_handle_pbdma_intr(g, &g->fifo, pbdma_id, RC_NO); + pbdma_stat = gk20a_readl(g, fifo_pbdma_status_r(pbdma_id)); chan_stat = fifo_pbdma_status_chan_status_v(pbdma_stat); - gk20a_dbg_info("wait preempt pbdma"); - if (chan_stat == fifo_pbdma_status_chan_status_valid_v() || chan_stat == @@ -473,26 +464,36 @@ static int gv11b_fifo_poll_pbdma_chan_status(struct gk20a *g, u32 id, } static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, - u32 engine_idx, u32 *reset_eng_bitmask, + u32 act_eng_id, u32 *reset_eng_bitmask, unsigned int timeout_rc_type) { struct nvgpu_timeout timeout; - unsigned long delay = GR_IDLE_CHECK_DEFAULT; + unsigned long delay = GR_IDLE_CHECK_DEFAULT; /* in micro seconds */ u32 eng_stat; u32 ctx_stat; int ret = -EBUSY; + bool stall_intr = false; + /* timeout in milli seconds */ nvgpu_timeout_init(g, &timeout, g->ops.fifo.get_preempt_timeout(g), NVGPU_TIMER_CPU_TIMER); + nvgpu_log(g, gpu_dbg_info, "wait preempt act engine id: %u", + act_eng_id); /* Check if ch/tsg has saved off the engine or if ctxsw is hung */ do { - eng_stat = gk20a_readl(g, fifo_engine_status_r(engine_idx)); + eng_stat = gk20a_readl(g, fifo_engine_status_r(act_eng_id)); ctx_stat = fifo_engine_status_ctx_status_v(eng_stat); + if (gv11b_mc_is_stall_and_eng_intr_pending(g, act_eng_id)) { + stall_intr = true; + nvgpu_log(g, gpu_dbg_info | gpu_dbg_intr, + "stall intr set, " + "preemption will not finish"); + } if (ctx_stat == fifo_engine_status_ctx_status_ctxsw_switch_v()) { - gk20a_dbg_info("engine save hasn't started yet"); + /* Eng save hasn't started yet. Continue polling */ } else if (ctx_stat == fifo_engine_status_ctx_status_valid_v() || @@ -500,14 +501,12 @@ static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, fifo_engine_status_ctx_status_ctxsw_save_v()) { if (id == fifo_engine_status_id_v(eng_stat)) { - if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { - /* called from recovery, eng seems to be hung */ - *reset_eng_bitmask |= BIT(engine_idx); + if (stall_intr || + timeout_rc_type == PREEMPT_TIMEOUT_NORC) { + /* preemption will not finish */ + *reset_eng_bitmask |= BIT(act_eng_id); ret = 0; break; - } else { - gk20a_dbg_info("wait preempt engine. " - "ctx_status (valid/save)=%u", ctx_stat); } } else { /* context is not running on the engine */ @@ -520,14 +519,12 @@ static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, if (id == fifo_engine_status_next_id_v(eng_stat)) { - if (timeout_rc_type == PREEMPT_TIMEOUT_NORC) { - /* called from recovery, eng seems to be hung */ - *reset_eng_bitmask |= BIT(engine_idx); + if (stall_intr || + timeout_rc_type == PREEMPT_TIMEOUT_NORC) { + /* preemption will not finish */ + *reset_eng_bitmask |= BIT(act_eng_id); ret = 0; break; - } else { - gk20a_dbg_info("wait preempt engine. " - "ctx_status (load)=%u", ctx_stat); } } else { /* context is not running on the engine */ @@ -540,7 +537,7 @@ static int gv11b_fifo_poll_eng_ctx_status(struct gk20a *g, u32 id, ret = 0; break; } - usleep_range(delay, delay * 2); + nvgpu_usleep_range(delay, delay * 2); delay = min_t(unsigned long, delay << 1, GR_IDLE_CHECK_MAX); } while (!nvgpu_timeout_expired_msg(&timeout, @@ -712,7 +709,7 @@ static int gv11b_fifo_poll_runlist_preempt_pending(struct gk20a *g, break; } - usleep_range(delay, delay * 2); + nvgpu_usleep_range(delay, delay * 2); delay = min_t(unsigned long, delay << 1, GR_IDLE_CHECK_MAX); } while (!nvgpu_timeout_expired_msg(&timeout, @@ -758,7 +755,7 @@ int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, f->runlist_info[runlist_id].reset_eng_bitmask = 0; - for_each_set_bit(act_eng_id, &runlist_served_engines, f->num_engines) { + for_each_set_bit(act_eng_id, &runlist_served_engines, f->max_engines) { func_ret = gv11b_fifo_poll_eng_ctx_status(g, tsgid, act_eng_id, &f->runlist_info[runlist_id].reset_eng_bitmask, -- cgit v1.2.2