From 418f31cd91a5c3ca45f0920ed64205def49c8a80 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Tue, 6 Mar 2018 10:43:16 -0800 Subject: gpu: nvgpu: Enable IO coherency on GV100 This reverts commit 848af2ce6de6140323a6ffe3075bf8021e119434. This is a revert of a revert, etc, etc. It re-enables IO coherence again. JIRA EVLR-2333 Change-Id: Ibf97dce2f892e48a1200a06cd38a1c5d9603be04 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1669722 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/fifo_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index feed2002..9e60d9f7 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -101,12 +101,14 @@ void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) c->runqueue_sel) | ram_rl_entry_chan_userd_target_f( nvgpu_aperture_mask(g, &g->fifo.userd, - ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(), - ram_rl_entry_chan_userd_target_vid_mem_v())) | + ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(), + ram_rl_entry_chan_userd_target_sys_mem_coh_v(), + ram_rl_entry_chan_userd_target_vid_mem_v())) | ram_rl_entry_chan_inst_target_f( nvgpu_aperture_mask(g, &c->inst_block, - ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(), - ram_rl_entry_chan_inst_target_vid_mem_v())); + ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(), + ram_rl_entry_chan_inst_target_sys_mem_coh_v(), + ram_rl_entry_chan_inst_target_vid_mem_v())); addr_lo = u64_lo32(c->userd_iova) >> ram_rl_entry_chan_userd_ptr_align_shift_v(); -- cgit v1.2.2