From da03aa782535e77e221a3c27b0676fe9c1c7980c Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 6 Jul 2018 10:03:31 -0700 Subject: gpu: nvgpu: Move programming FB phys access to FB FB physical access register for simulation was programmed in GR implementation. Move it to FB where it belongs. JIRA NVGPU-714 Change-Id: Ic5146a61c7d45eadffdb4f3b6b08906bfcdbc224 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1772915 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/fb_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 39903405..d6e621eb 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -68,6 +68,12 @@ void gv11b_fb_init_fs_state(struct gk20a *g) nvgpu_log(g, gpu_dbg_info, "mmu active ltcs %u", fb_mmu_num_active_ltcs_count_v( gk20a_readl(g, fb_mmu_num_active_ltcs_r()))); + + if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { + /* Bypass MMU check for non-secure boot. For + * secure-boot,this register write has no-effect */ + gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffffU); + } } void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr) -- cgit v1.2.2