From 6f24a7666045b25072282d4c29ff190b7af33e59 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Thu, 2 Jun 2016 09:44:13 +0530 Subject: gpu: nvgpu: Add multiple engine and runlist support This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt support for Volta GPU series 5) Removed hard coded engine_id logic and made generic way 6) Code cleanup for readability JIRA DNVGPU-26 Change-Id: Ief3b586ff3d9f492f0277243b2a94952bab48786 Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1156023 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 drivers/gpu/nvgpu/gv11b/ce_gv11b.c (limited to 'drivers/gpu/nvgpu/gv11b/ce_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c new file mode 100644 index 00000000..961054e0 --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -0,0 +1,27 @@ +/* + * Volta GPU series Copy Engine. + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. + */ + +#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ +#include "hw_ce_gv11b.h" +#include "gp10b/ce_gp10b.h" +#include "ce_gv11b.h" + +void gv11b_init_ce(struct gpu_ops *gops) +{ + gp10b_init_ce(gops); +} -- cgit v1.2.2 From 4b09997772f406d16945016ff4581c7c992faeab Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Thu, 12 Jan 2017 13:01:36 -0800 Subject: nvgpu: gpu: HW header update for Volta Similar HW header update as has been done for all the other chips. HW header files are located under: drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/ And can be included like so: #include Bug 1799159 Change-Id: If39bd71480a34f85bf25f4c36aec0f8f6de4dc9f Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1284433 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/ce_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index 961054e0..efe443cc 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -1,7 +1,7 @@ /* * Volta GPU series Copy Engine. * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,9 +16,10 @@ * this program. */ -#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ -#include "hw_ce_gv11b.h" +#include "gk20a/gk20a.h" + #include "gp10b/ce_gp10b.h" + #include "ce_gv11b.h" void gv11b_init_ce(struct gpu_ops *gops) -- cgit v1.2.2 From f525ff15c4e8b5994201585ad584237b62bf3083 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 28 Jun 2017 10:05:04 -0700 Subject: gpu: nvgpu: gv11b: add ce interrupt handling Added handling for below ce interrupts -INVALID_CONFIG interrupt will be generated if a floorswept PCE is assigned to a valid LCE in the NV_CE_PCE2LCE_CONFIG registers. This is a fatal error and the LCE will have to be reset to get back to a working state. -MTHD_BUFFER_FAULT interrupt will be triggered if any access to a method buffer during context load or save encounters a fault. This is a fatal interrupt and will require at least the LCE to be reset before operations can start again, if not the entire GPU. JIRA GPUT19X-12 JIRA GPUT19X-46 Change-Id: I2eeefc4e634f5bf53f20933c493c7594fe0ea755 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1510298 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 39 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/ce_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index efe443cc..1ba009bd 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -16,13 +16,52 @@ * this program. */ +#include "nvgpu/log.h" + #include "gk20a/gk20a.h" #include "gp10b/ce_gp10b.h" #include "ce_gv11b.h" +#include + +static void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) +{ + u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); + u32 clear_intr = 0; + + nvgpu_log(g, gpu_dbg_intr, "ce isr 0x%08x 0x%08x", ce_intr, inst_id); + + /* An INVALID_CONFIG interrupt will be generated if a floorswept + * PCE is assigned to a valid LCE in the NV_CE_PCE2LCE_CONFIG + * registers. This is a fatal error and the LCE will have to be + * reset to get back to a working state. + */ + if (ce_intr & ce_intr_status_invalid_config_pending_f()) { + nvgpu_log(g, gpu_dbg_intr, + "ce: inst %d: invalid config", inst_id); + clear_intr |= ce_intr_status_invalid_config_reset_f(); + } + + /* A MTHD_BUFFER_FAULT interrupt will be triggered if any access + * to a method buffer during context load or save encounters a fault. + * This is a fatal interrupt and will require at least the LCE to be + * reset before operations can start again, if not the entire GPU. + */ + if (ce_intr & ce_intr_status_mthd_buffer_fault_pending_f()) { + nvgpu_log(g, gpu_dbg_intr, + "ce: inst %d: mthd buffer fault", inst_id); + clear_intr |= ce_intr_status_mthd_buffer_fault_reset_f(); + } + + gk20a_writel(g, ce_intr_status_r(inst_id), clear_intr); + + gp10b_ce_isr(g, inst_id, pri_base); +} + void gv11b_init_ce(struct gpu_ops *gops) { gp10b_init_ce(gops); + gops->ce2.isr_stall = gv11b_ce_isr; } -- cgit v1.2.2 From 5a57be6ba1d491b4a3258281c82345fdb4a83675 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 30 Jun 2017 14:07:38 -0700 Subject: gpu: nvgpu: gv11b: init get_num_pce ce ops Implement get_num_pce ce ops to get number of physical copy engines. This is required to calculate eng method buffer size JIRA GPUT19X-46 Change-Id: I5a37eb26ec11bc358700d1761cfdb6ca060e4287 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1511788 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/ce_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index 1ba009bd..0bbd05b6 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -17,6 +17,7 @@ */ #include "nvgpu/log.h" +#include "nvgpu/bitops.h" #include "gk20a/gk20a.h" @@ -26,6 +27,19 @@ #include +static u32 gv11b_ce_get_num_pce(struct gk20a *g) +{ + /* register contains a bitmask indicating which physical copy + * engines are present (and not floorswept). + */ + u32 num_pce; + u32 ce_pce_map = gk20a_readl(g, ce_pce_map_r()); + + num_pce = get_count_order(ce_pce_map) + 1; + nvgpu_log_info(g, "num PCE: %d", num_pce); + return num_pce; +} + static void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) { u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); @@ -64,4 +78,5 @@ void gv11b_init_ce(struct gpu_ops *gops) { gp10b_init_ce(gops); gops->ce2.isr_stall = gv11b_ce_isr; + gops->ce2.get_num_pce = gv11b_ce_get_num_pce; } -- cgit v1.2.2 From 2f6d321390a98ace1e52f21c6a399e06b3fe71e7 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 7 Mar 2017 12:16:07 -0800 Subject: gpu: nvgpu: gv11b: add mmu fault handling HUB reports following memory sub-system interrupts: a) ACCESS_COUNTER_NOTIFY: GET != PUT for access counter notify buffer b) ACCESS_COUNTER_ERROR: HUB received a NACK (BAR2 fault) when writing the notify buffer out to memory c) MMU_ECC_UNCORRECTED_ERROR_NOTIFY: Uncorrected ECC error detected by HUB MMU d) MMU_REPLAYABLE_FAULT_NOTIFY: GET != PUT for replayable fault buffer e) MMU_REPLAYABLE_FAULT_OVERFLOW: Overflow when writing to the replayable fault buffer f) MMU_NONREPLAYABLE_FAULT_NOTIFY: GET != PUT for non-replayable fault buffer g) MMU_NONREPLAYABLE_FAULT_OVERFLOW: Overflow when writing to the non-replayable fault buffer h) MMU_OTHER_FAULT_NOTIFY: All other fault notifications from MMU This change is to : -Detect other fault notify -Copy fault info from fault snap register for other fault notify interrupt -Detect and handle nonreplay/replay fault notify and fault overflow -Copy fault info from fault buffer for nonreplay/replay fault -Print fault info JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: Ifa08a4ebcd119a7d81c2eae3f52dc825d1ce3898 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1493394 Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/ce_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index 0bbd05b6..af87f990 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -26,6 +26,7 @@ #include "ce_gv11b.h" #include +#include static u32 gv11b_ce_get_num_pce(struct gk20a *g) { @@ -74,6 +75,25 @@ static void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) gp10b_ce_isr(g, inst_id, pri_base); } +void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g) +{ + u32 reg_val, num_lce, lce, clear_intr; + + reg_val = gk20a_readl(g, top_num_ces_r()); + num_lce = top_num_ces_value_v(reg_val); + nvgpu_log_info(g, "num LCE: %d", num_lce); + + for (lce = 0; lce < num_lce; lce++) { + reg_val = gk20a_readl(g, ce_intr_status_r(lce)); + if (reg_val & ce_intr_status_mthd_buffer_fault_pending_f()) { + nvgpu_log(g, gpu_dbg_intr, + "ce: lce %d: mthd buffer fault", lce); + clear_intr = ce_intr_status_mthd_buffer_fault_reset_f(); + gk20a_writel(g, ce_intr_status_r(lce), clear_intr); + } + } +} + void gv11b_init_ce(struct gpu_ops *gops) { gp10b_init_ce(gops); -- cgit v1.2.2 From 66fb130bfdf12175c117f36737503b1b5f33d42e Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 15 May 2017 16:33:41 -0700 Subject: gpu: nvgpu: gv11b: recover from replay and ce mmu fault Fix pte valid bit for replayable fault and ce fault JIRA GPUT19X-12 Change-Id: I77a7a452d9b5b304f182e120e8d75959d46d4422 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1515538 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/ce_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index af87f990..9716c6d6 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -75,14 +75,23 @@ static void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) gp10b_ce_isr(g, inst_id, pri_base); } -void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g) +u32 gv11b_ce_get_num_lce(struct gk20a *g) { - u32 reg_val, num_lce, lce, clear_intr; + u32 reg_val, num_lce; reg_val = gk20a_readl(g, top_num_ces_r()); num_lce = top_num_ces_value_v(reg_val); nvgpu_log_info(g, "num LCE: %d", num_lce); + return num_lce; +} + +void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g) +{ + u32 reg_val, num_lce, lce, clear_intr; + + num_lce = gv11b_ce_get_num_lce(g); + for (lce = 0; lce < num_lce; lce++) { reg_val = gk20a_readl(g, ce_intr_status_r(lce)); if (reg_val & ce_intr_status_mthd_buffer_fault_pending_f()) { -- cgit v1.2.2 From 3c556c5e9573ffa69bfe64ed1401ed4a9141acb3 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Tue, 27 Jun 2017 15:09:58 -0700 Subject: gpu: nvgpu: gv11b: Reorg ce2 HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the ce2 sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ia2d715a471d7e23420691a461e9442780176ea13 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1509633 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/ce_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index 9716c6d6..8bf636b1 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -28,7 +28,7 @@ #include #include -static u32 gv11b_ce_get_num_pce(struct gk20a *g) +u32 gv11b_ce_get_num_pce(struct gk20a *g) { /* register contains a bitmask indicating which physical copy * engines are present (and not floorswept). @@ -41,7 +41,7 @@ static u32 gv11b_ce_get_num_pce(struct gk20a *g) return num_pce; } -static void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) +void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) { u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); u32 clear_intr = 0; @@ -102,10 +102,3 @@ void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g) } } } - -void gv11b_init_ce(struct gpu_ops *gops) -{ - gp10b_init_ce(gops); - gops->ce2.isr_stall = gv11b_ce_isr; - gops->ce2.get_num_pce = gv11b_ce_get_num_pce; -} -- cgit v1.2.2 From a42d6029a5afdf4fb2b9538a56808fbf3908a8ed Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 23 Aug 2017 10:04:58 -0700 Subject: gpu: nvgpu: gv11b: correct logic to get num of pce Correct the logic to get number of physical copy engines supported in gv11b. Change-Id: I02e0628364d056121d08dfcd0ddfb0c013207d4b Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1544207 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Seema Khowala Reviewed-by: Alex Waterman Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv11b/ce_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index 8bf636b1..4f611799 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -36,7 +36,7 @@ u32 gv11b_ce_get_num_pce(struct gk20a *g) u32 num_pce; u32 ce_pce_map = gk20a_readl(g, ce_pce_map_r()); - num_pce = get_count_order(ce_pce_map) + 1; + num_pce = hweight32(ce_pce_map); nvgpu_log_info(g, "num PCE: %d", num_pce); return num_pce; } -- cgit v1.2.2 From d61643c0200983dc340d37962bb0a3ca900a3e97 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 25 Sep 2017 08:59:28 -0700 Subject: gpu: nvgpu: gv11b: Change license for common files to MIT Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity Reviewed-by: David Martinez Nieto Reviewed-by: Seshendra Gadagottu Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/ce_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index 4f611799..86518ac7 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -3,17 +3,23 @@ * * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. * - * You should have received a copy of the GNU General Public License along with - * this program. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include "nvgpu/log.h" -- cgit v1.2.2