From 66fb130bfdf12175c117f36737503b1b5f33d42e Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 15 May 2017 16:33:41 -0700 Subject: gpu: nvgpu: gv11b: recover from replay and ce mmu fault Fix pte valid bit for replayable fault and ce fault JIRA GPUT19X-12 Change-Id: I77a7a452d9b5b304f182e120e8d75959d46d4422 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1515538 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv11b/ce_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index af87f990..9716c6d6 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c @@ -75,14 +75,23 @@ static void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) gp10b_ce_isr(g, inst_id, pri_base); } -void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g) +u32 gv11b_ce_get_num_lce(struct gk20a *g) { - u32 reg_val, num_lce, lce, clear_intr; + u32 reg_val, num_lce; reg_val = gk20a_readl(g, top_num_ces_r()); num_lce = top_num_ces_value_v(reg_val); nvgpu_log_info(g, "num LCE: %d", num_lce); + return num_lce; +} + +void gv11b_ce_mthd_buffer_fault_in_bar2_fault(struct gk20a *g) +{ + u32 reg_val, num_lce, lce, clear_intr; + + num_lce = gv11b_ce_get_num_lce(g); + for (lce = 0; lce < num_lce; lce++) { reg_val = gk20a_readl(g, ce_intr_status_r(lce)); if (reg_val & ce_intr_status_mthd_buffer_fault_pending_f()) { -- cgit v1.2.2