From 5d30a5cda37ca349b4d9cb7e1985c7a0849001b6 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 6 Sep 2018 20:44:27 +0530 Subject: gpu: nvgpu: ACR code refactor -Created struct nvgpu_acr to hold acr module related member within single struct which are currently spread across multiple structs like nvgpu_pmu, pmu_ops & gk20a. -Created struct hs_flcn_bl struct to hold ACR HS bootloader specific members -Created struct hs_acr to hold ACR ucode specific members like bootloader data using struct hs_flcn_bl, acr type & falcon info on which ACR ucode need to run. -Created acr ops under struct nvgpu_acr to perform ACR specific operation, currently ACR ops were part PMU which caused to have always dependence on PMU even though ACR was not executing on PMU. -Added acr_remove_support ops which will be called as part of gk20a_remove_support() method, earlier acr cleanup was part of pmu remove_support method. -Created define for ACR types, -Ops acr_sw_init() function helps to set ACR properties statically for chip currently in execution & assign ops to point to needed functions as per chip. -Ops acr_sw_init execute at early as nvgpu_init_mm_support calls acr function to alloc blob space. -Created ops to fill bootloader descriptor & to patch WPR info to ACR uocde based on interfaces used to bootstrap ACR ucode. -Created function gm20b_bootstrap_hs_acr() function which is now common HAL for all chips to bootstrap ACR, earlier had 3 different function for gm20b/gp10b, gv11b & for all dgpu based on interface needed. -Removed duplicate code for falcon engine wherever common falcon code can be used. -Removed ACR code dependent on PMU & made changes to use from nvgpu_acr. JIRA NVGPU-1148 Change-Id: I39951d2fc9a0bb7ee6057e0fa06da78045d47590 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1813231 GVS: Gerrit_Virtual_Submit Reviewed-by: svc-misra-checker Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv11b/acr_gv11b.c | 87 +++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) (limited to 'drivers/gpu/nvgpu/gv11b/acr_gv11b.c') diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c index f5ca144a..de2502ce 100644 --- a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c @@ -38,6 +38,7 @@ #include "acr_gv11b.h" #include "pmu_gv11b.h" #include "gm20b/mm_gm20b.h" +#include "gm20b/pmu_gm20b.h" #include "gm20b/acr_gm20b.h" #include "gp106/acr_gp106.h" @@ -68,6 +69,8 @@ void gv11b_setup_apertures(struct gk20a *g) struct mm_gk20a *mm = &g->mm; struct nvgpu_mem *inst_block = &mm->pmu.inst_block; + nvgpu_log_fn(g, " "); + /* setup apertures - virtual */ gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), pwr_fbif_transcfg_mem_type_physical_f() | @@ -91,3 +94,87 @@ void gv11b_setup_apertures(struct gk20a *g) pwr_fbif_transcfg_mem_type_physical_f() | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); } + +int gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g, struct nvgpu_acr *acr, + struct hs_acr *acr_desc, bool is_recovery) +{ + struct nvgpu_firmware *acr_fw = acr_desc->acr_fw; + struct acr_fw_header *acr_fw_hdr = NULL; + struct bin_hdr *acr_fw_bin_hdr = NULL; + struct flcn_acr_desc_v1 *acr_dmem_desc; + u32 *acr_ucode_header = NULL; + u32 *acr_ucode_data = NULL; + + nvgpu_log_fn(g, " "); + + if (is_recovery) { + acr_desc->acr_dmem_desc_v1->nonwpr_ucode_blob_size = 0U; + } else { + acr_fw_bin_hdr = (struct bin_hdr *)acr_fw->data; + acr_fw_hdr = (struct acr_fw_header *) + (acr_fw->data + acr_fw_bin_hdr->header_offset); + + acr_ucode_data = (u32 *)(acr_fw->data + + acr_fw_bin_hdr->data_offset); + acr_ucode_header = (u32 *)(acr_fw->data + + acr_fw_hdr->hdr_offset); + + /* During recovery need to update blob size as 0x0*/ + acr_desc->acr_dmem_desc_v1 = (struct flcn_acr_desc_v1 *) + ((u8 *)(acr_desc->acr_ucode.cpu_va) + + acr_ucode_header[2U]); + + /* Patch WPR info to ucode */ + acr_dmem_desc = (struct flcn_acr_desc_v1 *) + &(((u8 *)acr_ucode_data)[acr_ucode_header[2U]]); + + acr_dmem_desc->nonwpr_ucode_blob_start = + nvgpu_mem_get_addr(g, &g->acr.ucode_blob); + acr_dmem_desc->nonwpr_ucode_blob_size = + g->acr.ucode_blob.size; + acr_dmem_desc->regions.no_regions = 1U; + acr_dmem_desc->wpr_offset = 0U; + } + + return 0; +} + +static void gv11b_acr_default_sw_init(struct gk20a *g, struct hs_acr *hs_acr) +{ + struct hs_flcn_bl *hs_bl = &hs_acr->acr_hs_bl; + + nvgpu_log_fn(g, " "); + + hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE; + + hs_acr->acr_type = ACR_DEFAULT; + hs_acr->acr_fw_name = HSBIN_ACR_UCODE_IMAGE; + + hs_acr->ptr_bl_dmem_desc = &hs_acr->bl_dmem_desc_v1; + hs_acr->bl_dmem_desc_size = sizeof(struct flcn_bl_dmem_desc_v1); + + hs_acr->acr_flcn = &g->pmu_flcn; + hs_acr->acr_flcn_setup_hw_and_bl_bootstrap = + gm20b_pmu_setup_hw_and_bl_bootstrap; +} + +void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr) +{ + nvgpu_log_fn(g, " "); + + acr->g = g; + + acr->bootstrap_owner = LSF_FALCON_ID_PMU; + acr->max_supported_lsfm = MAX_SUPPORTED_LSFM; + + gv11b_acr_default_sw_init(g, &acr->acr); + + acr->get_wpr_info = gm20b_wpr_info; + acr->alloc_blob_space = gv11b_alloc_blob_space; + acr->bootstrap_hs_acr = gm20b_bootstrap_hs_acr; + acr->patch_wpr_info_to_ucode = gv11b_acr_patch_wpr_info_to_ucode; + acr->acr_fill_bl_dmem_desc = + gp106_acr_fill_bl_dmem_desc; + + acr->remove_support = gm20b_remove_acr_support; +} -- cgit v1.2.2