From de8e057f7eebcfe676278826ab457bf86b1b36fd Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 3 Aug 2017 21:43:50 -0700 Subject: gpu: nvgpu: GV100 support Adds support of GV100 up to devinit. JIRA: EVLR-1693 Change-Id: Ic7aa5f1c20714e05954139f143abb6a3459858fc Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1532747 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv100/fb_gv100.c | 58 +++++ drivers/gpu/nvgpu/gv100/fb_gv100.h | 22 ++ drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c | 38 +++ drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h | 28 +++ drivers/gpu/nvgpu/gv100/gv100.h | 26 ++ drivers/gpu/nvgpu/gv100/hal_gv100.c | 441 +++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv100/hal_gv100.h | 21 ++ drivers/gpu/nvgpu/gv100/mm_gv100.c | 41 +++ drivers/gpu/nvgpu/gv100/mm_gv100.h | 23 ++ 9 files changed, 698 insertions(+) create mode 100644 drivers/gpu/nvgpu/gv100/fb_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/fb_gv100.h create mode 100644 drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h create mode 100644 drivers/gpu/nvgpu/gv100/gv100.h create mode 100644 drivers/gpu/nvgpu/gv100/hal_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/hal_gv100.h create mode 100644 drivers/gpu/nvgpu/gv100/mm_gv100.c create mode 100644 drivers/gpu/nvgpu/gv100/mm_gv100.h (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c new file mode 100644 index 00000000..a3785266 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c @@ -0,0 +1,58 @@ +/* + * GV100 FB + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include +#include +#include +#include + +#include "gk20a/gk20a.h" +#include "gv11b/fb_gv11b.h" +#include "gv100/fb_gv100.h" + +#include + +#define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */ +#define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */ + +static void gv100_fb_reset(struct gk20a *g) +{ + u32 val; + int retries = HW_SCRUB_TIMEOUT_MAX / HW_SCRUB_TIMEOUT_DEFAULT; + + nvgpu_info(g, "reset gv100 fb"); + + /* wait for memory to be accessible */ + do { + u32 w = gk20a_readl(g, fb_niso_scrub_status_r()); + if (fb_niso_scrub_status_flag_v(w)) { + nvgpu_info(g, "done"); + break; + } + nvgpu_udelay(HW_SCRUB_TIMEOUT_DEFAULT); + } while (--retries); + + val = gk20a_readl(g, fb_mmu_priv_level_mask_r()); + val &= ~fb_mmu_priv_level_mask_write_violation_m(); + gk20a_writel(g, fb_mmu_priv_level_mask_r(), val); +} + +void gv100_init_fb(struct gpu_ops *gops) +{ + gv11b_init_fb(gops); + gops->fb.reset = gv100_fb_reset; +} diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.h b/drivers/gpu/nvgpu/gv100/fb_gv100.h new file mode 100644 index 00000000..b234fa13 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.h @@ -0,0 +1,22 @@ +/* + * GV100 FB + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_GV100_FB +#define _NVGPU_GV100_FB + +struct gpu_ops; + +void gv100_init_fb(struct gpu_ops *gops); +#endif diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c new file mode 100644 index 00000000..2e605cce --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.c @@ -0,0 +1,38 @@ +/* + * GV100 Graphics Context + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" +#include "gr_ctx_gv100.h" + +int gr_gv100_get_netlist_name(struct gk20a *g, int index, char *name) +{ + u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; + + switch (ver) { + case NVGPU_GPUID_GV100: + sprintf(name, "%s/%s", "gv100", + GV100_NETLIST_IMAGE_FW_NAME); + break; + default: + nvgpu_err(g, "no support for GPUID %x", ver); + } + + return 0; +} + +bool gr_gv100_is_firmware_defined(void) +{ + return true; +} diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h new file mode 100644 index 00000000..122e750f --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __GR_CTX_GV100_H__ +#define __GR_CTX_GV100_H__ + +#include "gk20a/gr_ctx_gk20a.h" +#include "nvgpu_gpuid_t19x.h" + +/* production netlist, one and only one from below */ +#define GV100_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_D + +int gr_gv100_get_netlist_name(struct gk20a *g, int index, char *name); +bool gr_gv100_is_firmware_defined(void); + +#endif /*__GR_CTX_GV100_H__*/ diff --git a/drivers/gpu/nvgpu/gv100/gv100.h b/drivers/gpu/nvgpu/gv100/gv100.h new file mode 100644 index 00000000..eeea64a4 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gv100.h @@ -0,0 +1,26 @@ +/* + * GV100 Graphics + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef GV100_H +#define GV100_H + +#include "gk20a/gk20a.h" + +int gv100_init_gpu_characteristics(struct gk20a *g); + +#endif /* GV11B_H */ diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c new file mode 100644 index 00000000..337c607f --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -0,0 +1,441 @@ +/* + * GV100 Tegra HAL interface + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#include +#include + +#include "gk20a/gk20a.h" +#include "gk20a/fifo_gk20a.h" +#include "gk20a/ctxsw_trace_gk20a.h" +#include "gk20a/fecs_trace_gk20a.h" +#include "gk20a/css_gr_gk20a.h" +#include "gk20a/mc_gk20a.h" +#include "gk20a/dbg_gpu_gk20a.h" +#include "gk20a/bus_gk20a.h" +#include "gk20a/pramin_gk20a.h" +#include "gk20a/flcn_gk20a.h" +#include "gk20a/regops_gk20a.h" + +#include "gm20b/ltc_gm20b.h" +#include "gm20b/gr_gm20b.h" +#include "gm20b/fifo_gm20b.h" + +#include "gp106/clk_gp106.h" +#include "gp106/clk_arb_gp106.h" +#include "gp106/pmu_gp106.h" + +#include "gm206/bios_gm206.h" +#include "gp106/therm_gp106.h" +#include "gp106/xve_gp106.h" +#include "gp106/clk_gp106.h" +#include "gp106/flcn_gp106.h" +#include "gp10b/ltc_gp10b.h" +#include "gp10b/therm_gp10b.h" +#include "gp10b/mc_gp10b.h" +#include "gp10b/ce_gp10b.h" +#include "gp10b/priv_ring_gp10b.h" +#include "gp10b/fifo_gp10b.h" +#include "gp10b/fecs_trace_gp10b.h" + +#include "gv11b/hal_gv11b.h" +#include "gv11b/gr_gv11b.h" +#include "gv11b/mc_gv11b.h" +#include "gv11b/ltc_gv11b.h" +#include "gv11b/gv11b.h" +#include "gv11b/ce_gv11b.h" +#include "gv100/gr_ctx_gv100.h" +#include "gv100/mm_gv100.h" +#include "gv11b/pmu_gv11b.h" +#include "gv100/fb_gv100.h" +#include "gv11b/fifo_gv11b.h" +#include "gv11b/gv11b_gating_reglist.h" +#include "gv11b/regops_gv11b.h" +#include "gv11b/subctx_gv11b.h" + +#include "gv100.h" +#include "hal_gv100.h" + +#include +#include + +#include +#include +#include +#include +#include + +static int gv100_get_litter_value(struct gk20a *g, int value) +{ + int ret = EINVAL; + switch (value) { + case GPU_LIT_NUM_GPCS: + ret = proj_scal_litter_num_gpcs_v(); + break; + case GPU_LIT_NUM_PES_PER_GPC: + ret = proj_scal_litter_num_pes_per_gpc_v(); + break; + case GPU_LIT_NUM_ZCULL_BANKS: + ret = proj_scal_litter_num_zcull_banks_v(); + break; + case GPU_LIT_NUM_TPC_PER_GPC: + ret = proj_scal_litter_num_tpc_per_gpc_v(); + break; + case GPU_LIT_NUM_SM_PER_TPC: + ret = proj_scal_litter_num_sm_per_tpc_v(); + break; + case GPU_LIT_NUM_FBPS: + ret = proj_scal_litter_num_fbps_v(); + break; + case GPU_LIT_GPC_BASE: + ret = proj_gpc_base_v(); + break; + case GPU_LIT_GPC_STRIDE: + ret = proj_gpc_stride_v(); + break; + case GPU_LIT_GPC_SHARED_BASE: + ret = proj_gpc_shared_base_v(); + break; + case GPU_LIT_TPC_IN_GPC_BASE: + ret = proj_tpc_in_gpc_base_v(); + break; + case GPU_LIT_TPC_IN_GPC_STRIDE: + ret = proj_tpc_in_gpc_stride_v(); + break; + case GPU_LIT_TPC_IN_GPC_SHARED_BASE: + ret = proj_tpc_in_gpc_shared_base_v(); + break; + case GPU_LIT_PPC_IN_GPC_BASE: + ret = proj_ppc_in_gpc_base_v(); + case GPU_LIT_PPC_IN_GPC_STRIDE: + ret = proj_ppc_in_gpc_stride_v(); + break; + case GPU_LIT_ROP_BASE: + ret = proj_rop_base_v(); + break; + case GPU_LIT_ROP_STRIDE: + ret = proj_rop_stride_v(); + break; + case GPU_LIT_ROP_SHARED_BASE: + ret = proj_rop_shared_base_v(); + break; + case GPU_LIT_HOST_NUM_ENGINES: + ret = proj_host_num_engines_v(); + break; + case GPU_LIT_HOST_NUM_PBDMA: + ret = proj_host_num_pbdma_v(); + break; + case GPU_LIT_LTC_STRIDE: + ret = proj_ltc_stride_v(); + break; + case GPU_LIT_LTS_STRIDE: + ret = proj_lts_stride_v(); + break; + case GPU_LIT_NUM_FBPAS: + ret = proj_scal_litter_num_fbpas_v(); + break; + case GPU_LIT_FBPA_STRIDE: + ret = proj_fbpa_stride_v(); + break; + case GPU_LIT_SM_PRI_STRIDE: + ret = proj_sm_stride_v(); + break; + + default: + break; + } + + return ret; +} + +int gv100_init_gpu_characteristics(struct gk20a *g) +{ + struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics; + + int err; + + err = gk20a_init_gpu_characteristics(g); + if (err) + return err; + + gpu->flags |= + NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS; + + return 0; +} + + + +static const struct gpu_ops gv100_ops = { + .ltc = { + .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, + .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, + .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, + .init_cbc = NULL, + .init_fs_state = gv11b_ltc_init_fs_state, + .init_comptags = gp10b_ltc_init_comptags, + .cbc_ctrl = gm20b_ltc_cbc_ctrl, + .isr = gv11b_ltc_isr, + .cbc_fix_config = gv11b_ltc_cbc_fix_config, + .flush = gm20b_flush_ltc, + .set_enabled = gp10b_ltc_set_enabled, + }, + .ce2 = { + .isr_stall = gv11b_ce_isr, + .isr_nonstall = gp10b_ce_nonstall_isr, + .get_num_pce = gv11b_ce_get_num_pce, + }, + .fifo = { + .init_fifo_setup_hw = gv11b_init_fifo_setup_hw, + .bind_channel = channel_gm20b_bind, + .unbind_channel = channel_gv11b_unbind, + .disable_channel = gk20a_fifo_disable_channel, + .enable_channel = gk20a_fifo_enable_channel, + .alloc_inst = gk20a_fifo_alloc_inst, + .free_inst = gk20a_fifo_free_inst, + .setup_ramfc = channel_gv11b_setup_ramfc, + .channel_set_priority = gk20a_fifo_set_priority, + .channel_set_timeslice = gk20a_fifo_set_timeslice, + .default_timeslice_us = gk20a_fifo_default_timeslice_us, + .setup_userd = gk20a_fifo_setup_userd, + .userd_gp_get = gv11b_userd_gp_get, + .userd_gp_put = gv11b_userd_gp_put, + .userd_pb_get = gv11b_userd_pb_get, + .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, + .preempt_channel = gv11b_fifo_preempt_channel, + .preempt_tsg = gv11b_fifo_preempt_tsg, + .update_runlist = gk20a_fifo_update_runlist, + .trigger_mmu_fault = NULL, + .get_mmu_fault_info = NULL, + .wait_engine_idle = gk20a_fifo_wait_engine_idle, + .get_num_fifos = gv11b_fifo_get_num_fifos, + .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, + .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, + .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, + .force_reset_ch = gk20a_fifo_force_reset_ch, + .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, + .device_info_data_parse = gp10b_device_info_data_parse, + .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, + .init_engine_info = gk20a_fifo_init_engine_info, + .runlist_entry_size = ram_rl_entry_size_v, + .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry, + .get_ch_runlist_entry = gv11b_get_ch_runlist_entry, + .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, + .dump_pbdma_status = gk20a_dump_pbdma_status, + .dump_eng_status = gv11b_dump_eng_status, + .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc, + .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, + .is_preempt_pending = gv11b_fifo_is_preempt_pending, + .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, + .reset_enable_hw = gv11b_init_fifo_reset_enable_hw, + .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, + .handle_sched_error = gv11b_fifo_handle_sched_error, + .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, + .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, + .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers, + .deinit_eng_method_buffers = + gv11b_fifo_deinit_eng_method_buffers, + .tsg_bind_channel = gk20a_tsg_bind_channel, + .tsg_unbind_channel = gk20a_tsg_unbind_channel, +#ifdef CONFIG_TEGRA_GK20A_NVHOST + .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, + .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, + .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd, + .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, + .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, + .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, +#endif + .resetup_ramfc = NULL, + .device_info_fault_id = top_device_info_data_fault_id_enum_v, + .free_channel_ctx_header = gv11b_free_subctx_header, + .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg, + .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, + }, + .gr_ctx = { + .get_netlist_name = gr_gv100_get_netlist_name, + .is_fw_defined = gr_gv100_is_firmware_defined, + }, +#ifdef CONFIG_GK20A_CTXSW_TRACE + .fecs_trace = { + .alloc_user_buffer = gk20a_ctxsw_dev_ring_alloc, + .free_user_buffer = gk20a_ctxsw_dev_ring_free, + .mmap_user_buffer = gk20a_ctxsw_dev_mmap_buffer, + .init = gk20a_fecs_trace_init, + .deinit = gk20a_fecs_trace_deinit, + .enable = gk20a_fecs_trace_enable, + .disable = gk20a_fecs_trace_disable, + .is_enabled = gk20a_fecs_trace_is_enabled, + .reset = gk20a_fecs_trace_reset, + .flush = gp10b_fecs_trace_flush, + .poll = gk20a_fecs_trace_poll, + .bind_channel = gk20a_fecs_trace_bind_channel, + .unbind_channel = gk20a_fecs_trace_unbind_channel, + .max_entries = gk20a_gr_max_entries, + }, +#endif /* CONFIG_GK20A_CTXSW_TRACE */ + .pramin = { + .enter = gk20a_pramin_enter, + .exit = gk20a_pramin_exit, + .data032_r = pram_data032_r, + }, + .clk = { + .init_clk_support = gp106_init_clk_support, + .get_crystal_clk_hz = gp106_crystal_clk_hz, + .measure_freq = gp106_clk_measure_freq, + .suspend_clk_support = gp106_suspend_clk_support, + }, + .clk_arb = { + .get_arbiter_clk_domains = gp106_get_arbiter_clk_domains, + .get_arbiter_clk_range = gp106_get_arbiter_clk_range, + .get_arbiter_clk_default = gp106_get_arbiter_clk_default, + .get_current_pstate = nvgpu_clk_arb_get_current_pstate, + }, + .mc = { + .intr_enable = mc_gv11b_intr_enable, + .intr_unit_config = mc_gp10b_intr_unit_config, + .isr_stall = mc_gp10b_isr_stall, + .intr_stall = mc_gp10b_intr_stall, + .intr_stall_pause = mc_gp10b_intr_stall_pause, + .intr_stall_resume = mc_gp10b_intr_stall_resume, + .intr_nonstall = mc_gp10b_intr_nonstall, + .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, + .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, + .enable = gk20a_mc_enable, + .disable = gk20a_mc_disable, + .reset = gk20a_mc_reset, + .boot_0 = gk20a_mc_boot_0, + .is_intr1_pending = mc_gp10b_is_intr1_pending, + .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, + }, + .debug = { + .show_dump = gk20a_debug_show_dump, + }, + .dbg_session_ops = { + .exec_reg_ops = exec_regops_gk20a, + .dbg_set_powergate = dbg_set_powergate, + .check_and_set_global_reservation = + nvgpu_check_and_set_global_reservation, + .check_and_set_context_reservation = + nvgpu_check_and_set_context_reservation, + .release_profiler_reservation = + nvgpu_release_profiler_reservation, + .perfbuffer_enable = gk20a_perfbuf_enable_locked, + .perfbuffer_disable = gk20a_perfbuf_disable_locked, + }, + .bus = { + .init_hw = gk20a_bus_init_hw, + .isr = gk20a_bus_isr, + .read_ptimer = gk20a_read_ptimer, + .bar1_bind = NULL, + }, +#if defined(CONFIG_GK20A_CYCLE_STATS) + .css = { + .enable_snapshot = css_hw_enable_snapshot, + .disable_snapshot = css_hw_disable_snapshot, + .check_data_available = css_hw_check_data_available, + .set_handled_snapshots = css_hw_set_handled_snapshots, + .allocate_perfmon_ids = css_gr_allocate_perfmon_ids, + .release_perfmon_ids = css_gr_release_perfmon_ids, + }, +#endif + .xve = { + .sw_init = xve_sw_init_gp106, + .get_speed = xve_get_speed_gp106, + .set_speed = xve_set_speed_gp106, + .available_speeds = xve_available_speeds_gp106, + .xve_readl = xve_xve_readl_gp106, + .xve_writel = xve_xve_writel_gp106, + .disable_aspm = xve_disable_aspm_gp106, + .reset_gpu = xve_reset_gpu_gp106, +#if defined(CONFIG_PCI_MSI) + .rearm_msi = xve_rearm_msi_gp106, +#endif + .enable_shadow_rom = xve_enable_shadow_rom_gp106, + .disable_shadow_rom = xve_disable_shadow_rom_gp106, + }, + .falcon = { + .falcon_hal_sw_init = gp106_falcon_hal_sw_init, + }, + .priv_ring = { + .isr = gp10b_priv_ring_isr, + }, + .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, + .get_litter_value = gv100_get_litter_value, + .bios_init = gm206_bios_init, +}; + +int gv100_init_hal(struct gk20a *g) +{ + struct gpu_ops *gops = &g->ops; + struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + + gops->ltc = gv100_ops.ltc; + gops->ce2 = gv100_ops.ce2; + gops->clock_gating = gv100_ops.clock_gating; + gops->fifo = gv100_ops.fifo; + gops->gr_ctx = gv100_ops.gr_ctx; + gops->fecs_trace = gv100_ops.fecs_trace; + gops->pramin = gv100_ops.pramin; + gops->therm = gv100_ops.therm; + gops->mc = gv100_ops.mc; + gops->debug = gv100_ops.debug; + gops->dbg_session_ops = gv100_ops.dbg_session_ops; + gops->bus = gv100_ops.bus; +#if defined(CONFIG_GK20A_CYCLE_STATS) + gops->css = gv100_ops.css; +#endif + gops->xve = gv100_ops.xve; + gops->falcon = gv100_ops.falcon; + gops->priv_ring = gv100_ops.priv_ring; + + /* clocks */ + gops->clk.init_clk_support = gv100_ops.clk.init_clk_support; + gops->clk.get_crystal_clk_hz = gv100_ops.clk.get_crystal_clk_hz; + gops->clk.measure_freq = gv100_ops.clk.measure_freq; + gops->clk.suspend_clk_support = gv100_ops.clk.suspend_clk_support; + + /* Lone functions */ + gops->chip_init_gpu_characteristics = + gv100_ops.chip_init_gpu_characteristics; + gops->get_litter_value = gv100_ops.get_litter_value; + gops->bios_init = gv100_ops.bios_init; + + __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); + /* for now */ + __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); + + g->bootstrap_owner = LSF_FALCON_ID_SEC2; + + gv11b_init_gr(g); + gv100_init_fb(gops); + gv100_init_mm(gops); + gp106_init_pmu_ops(g); + + g->name = "gv10x"; + + c->twod_class = FERMI_TWOD_A; + c->threed_class = VOLTA_A; + c->compute_class = VOLTA_COMPUTE_A; + c->gpfifo_class = VOLTA_CHANNEL_GPFIFO_A; + c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; + c->dma_copy_class = VOLTA_DMA_COPY_A; + + return 0; +} diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.h b/drivers/gpu/nvgpu/gv100/hal_gv100.h new file mode 100644 index 00000000..a7c74db0 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.h @@ -0,0 +1,21 @@ +/* + * GV100 Tegra HAL interface + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_HAL_GV11B_H +#define _NVGPU_HAL_GV11B_H +struct gk20a; + +int gv100_init_hal(struct gk20a *gops); +#endif diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.c b/drivers/gpu/nvgpu/gv100/mm_gv100.c new file mode 100644 index 00000000..fbc5df79 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.c @@ -0,0 +1,41 @@ +/* + * GV100 memory management + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" +#include "gv11b/mm_gv11b.h" +#include "gv100/mm_gv100.h" + +#include + +static size_t gv100_mm_get_vidmem_size(struct gk20a *g) +{ + u32 range = gk20a_readl(g, fb_mmu_local_memory_range_r()); + u32 mag = fb_mmu_local_memory_range_lower_mag_v(range); + u32 scale = fb_mmu_local_memory_range_lower_scale_v(range); + u32 ecc = fb_mmu_local_memory_range_ecc_mode_v(range); + size_t bytes = ((size_t)mag << scale) * SZ_1M; + + if (ecc) + bytes = bytes / 16 * 15; + + return bytes; +} + +void gv100_init_mm(struct gpu_ops *gops) +{ + gv11b_init_mm(gops); + gops->mm.get_vidmem_size = gv100_mm_get_vidmem_size; + gops->mm.get_physical_addr_bits = NULL; +} diff --git a/drivers/gpu/nvgpu/gv100/mm_gv100.h b/drivers/gpu/nvgpu/gv100/mm_gv100.h new file mode 100644 index 00000000..ff1bc3df --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/mm_gv100.h @@ -0,0 +1,23 @@ +/* + * GV100 memory management + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef MM_GV100_H +#define MM_GV100_H + +struct gpu_ops; + +void gv100_init_mm(struct gpu_ops *gops); + +#endif -- cgit v1.2.2