From 89e0745fa024891b988508c3baa20c453230a80b Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 2 Apr 2018 19:10:42 +0530 Subject: gpu: nvgpu: handle misaligned_addr SM exception We right now do not handle misaligned_addr SM exception explicitly and hence we incorrectly initiate CILP on this exception Handle this exception explicitly in this sequence - - set error notifier first - clear the interrupt - return error from gr_gv11b_handle_warp_esr_error_misaligned_addr() so that RC recovery is triggered by gk20a_gr_isr() Ensure that the error value is propagated back to gk20a_gr_isr() correctly Use nvgpu_set_error_notifier_if_empty() to set error notifier since this will prevent overwriting of error notifier value in case gk20a_gr_isr() also tries to write to some error notifier value Bug 200388475 Jira NVGPU-554 Change-Id: I84c4d202a8068e738567ccd344e05d9d5f6ad2f0 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1686781 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index f0187dab..b38260a5 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -517,7 +517,7 @@ static const struct gpu_ops gv100_ops = { .check_ch_ctxsw_timeout = gk20a_fifo_check_ch_ctxsw_timeout, .channel_suspend = gk20a_channel_suspend, .channel_resume = gk20a_channel_resume, - .set_error_notifier = nvgpu_set_error_notifier, + .set_error_notifier = nvgpu_set_error_notifier_if_empty, .setup_sw = gk20a_init_fifo_setup_sw, #ifdef CONFIG_TEGRA_GK20A_NVHOST .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, -- cgit v1.2.2