From 77b806fe7e68e853676f7c4bad14349aba1affa5 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 16 Mar 2018 17:55:18 +0530 Subject: gpu: nvgpu: gv100: fix PMA list alignment in ctxsw buffer GV100 ucode is changed so that it expects LIST_nv_perf_pma_ctx_reg list in ctxsw buffer to be 256 byte aligned but same change is not applied to other chip ucodes ADD new HAL (*add_ctxsw_reg_perf_pma) to configure PMA register list and define a common HAL gr_gk20a_add_ctxsw_reg_perf_pma() for all other chips except GV100 Define a separate HAL for GV100 gr_gv100_add_ctxsw_reg_perf_pma() and fix the required alignment in this function Bug 1998067 Change-Id: Ie172fe90e2cdbac2509f2ece953cd8552e66fc56 Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1676655 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/gr_gv100.c | 10 ++++++++++ drivers/gpu/nvgpu/gv100/gr_gv100.h | 4 ++++ drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + 3 files changed, 15 insertions(+) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c index 3aed7a19..c6273733 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c @@ -373,3 +373,13 @@ int gr_gv100_add_ctxsw_reg_pm_fbpa(struct gk20a *g, *offset = off; return 0; } + +int gr_gv100_add_ctxsw_reg_perf_pma(struct ctxsw_buf_offset_map_entry *map, + struct aiv_list_gk20a *regs, + u32 *count, u32 *offset, + u32 max_cnt, u32 base, u32 mask) +{ + *offset = ALIGN(*offset, 256); + return gr_gk20a_add_ctxsw_reg_perf_pma(map, regs, + count, offset, max_cnt, base, mask); +} diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.h b/drivers/gpu/nvgpu/gv100/gr_gv100.h index e1174686..7b107db2 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.h +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.h @@ -39,4 +39,8 @@ int gr_gv100_add_ctxsw_reg_pm_fbpa(struct gk20a *g, u32 *count, u32 *offset, u32 max_cnt, u32 base, u32 num_fbpas, u32 stride, u32 mask); +int gr_gv100_add_ctxsw_reg_perf_pma(struct ctxsw_buf_offset_map_entry *map, + struct aiv_list_gk20a *regs, + u32 *count, u32 *offset, + u32 max_cnt, u32 base, u32 mask); #endif diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 08fc7c34..cfac8e0e 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -430,6 +430,7 @@ static const struct gpu_ops gv100_ops = { .handle_notify_pending = gk20a_gr_handle_notify_pending, .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, .add_ctxsw_reg_pm_fbpa = gr_gv100_add_ctxsw_reg_pm_fbpa, + .add_ctxsw_reg_perf_pma = gr_gv100_add_ctxsw_reg_perf_pma, }, .fb = { .reset = gv100_fb_reset, -- cgit v1.2.2