From 6b90684ceec6c32aed7491a059b3972b1f1be5f4 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Sat, 30 Dec 2017 13:04:19 -0800 Subject: gpu: nvgpu: vgpu: get virtual SMs mapping On gv11b we can have multiple SMs per TPC. Add sm_per_tpc in vgpu constants to properly dimension the virtual SM to TPC/GPC mapping in virtualization case. Use TEGRA_VGPU_CMD_GET_SMS_MAPPING to query current mapping. Bug 2039676 Change-Id: I817be18f9a28cfb9bd8af207d7d6341a2ec3994b Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/1631203 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/gr_gv100.c | 8 +++++--- drivers/gpu/nvgpu/gv100/gr_gv100.h | 4 ++-- 2 files changed, 7 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c index 430c7cd0..f90fd075 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c @@ -1,7 +1,7 @@ /* * GV100 GPU GR * - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -199,14 +199,14 @@ void gr_gv100_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) { } -void gr_gv100_init_sm_id_table(struct gk20a *g) +int gr_gv100_init_sm_id_table(struct gk20a *g) { u32 gpc, tpc, sm, pes, gtpc; u32 sm_id = 0; u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); u32 num_sm = sm_per_tpc * g->gr.tpc_count; int perf, maxperf; - int err; + int err = 0; unsigned long *gpc_tpc_mask; u32 *tpc_table, *gpc_table; @@ -217,6 +217,7 @@ void gr_gv100_init_sm_id_table(struct gk20a *g) if (!gpc_table || !tpc_table || !gpc_tpc_mask) { nvgpu_err(g, "Error allocating memory for sm tables"); + err = -ENOMEM; goto exit_build_table; } @@ -273,6 +274,7 @@ exit_build_table: nvgpu_kfree(g, gpc_table); nvgpu_kfree(g, tpc_table); nvgpu_kfree(g, gpc_tpc_mask); + return err; } void gr_gv100_load_tpc_mask(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.h b/drivers/gpu/nvgpu/gv100/gr_gv100.h index 612f76f9..690bba57 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.h +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.h @@ -1,7 +1,7 @@ /* * GV100 GPU GR * - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -28,7 +28,7 @@ void gr_gv100_bundle_cb_defaults(struct gk20a *g); void gr_gv100_cb_size_default(struct gk20a *g); void gr_gv100_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); -void gr_gv100_init_sm_id_table(struct gk20a *g); +int gr_gv100_init_sm_id_table(struct gk20a *g); void gr_gv100_program_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid); int gr_gv100_load_smid_config(struct gk20a *g); -- cgit v1.2.2