From 4efdc362175c67f93d3546727c8825686619c1cb Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 19 Sep 2018 12:23:05 +0530 Subject: gpu: nvgpu: ACR load split feature support -Added code to copy SEC2-RTOS ucode to non-wpr blob as part of prepare ucode blob. -Added code to setup & bootstrap GSP, as ACR-ASB needs ucode to execute on GSP falcon. -Defined LSF_FALCON_ID_GSPLITE for GSP falcon -Defined HSBIN_ACR_AHESASC_DBG/PROD_UCODE & HSBIN_ACR_ASB_DBG/PROD_UCODE to hold names of ACR AHESASC/ASB ucodes. -Added defines to hold name of SE2C RTOS ucodes JIRA NVGPUT-134 Change-Id: I824afed41f785a4ca0fb393bd023db5396c7a399 Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1790179 Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/gsp_gv100.c | 72 +++++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv100/gsp_gv100.h | 3 ++ 2 files changed, 75 insertions(+) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/gsp_gv100.c b/drivers/gpu/nvgpu/gv100/gsp_gv100.c index 6ea7ab71..d6d01b7f 100644 --- a/drivers/gpu/nvgpu/gv100/gsp_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gsp_gv100.c @@ -39,3 +39,75 @@ int gv100_gsp_reset(struct gk20a *g) return 0; } + +static int gsp_flcn_bl_bootstrap(struct gk20a *g, + struct nvgpu_falcon_bl_info *bl_info) +{ + struct mm_gk20a *mm = &g->mm; + u32 data = 0; + u32 status = 0; + + gk20a_writel(g, pgsp_falcon_itfen_r(), + gk20a_readl(g, pgsp_falcon_itfen_r()) | + pgsp_falcon_itfen_ctxen_enable_f()); + + gk20a_writel(g, pgsp_falcon_nxtctx_r(), + pgsp_falcon_nxtctx_ctxptr_f( + nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12U) | + pgsp_falcon_nxtctx_ctxvalid_f(1) | + nvgpu_aperture_mask(g, &mm->pmu.inst_block, + pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f(), + pgsp_falcon_nxtctx_ctxtgt_sys_coh_f(), + pgsp_falcon_nxtctx_ctxtgt_fb_f())); + + data = gk20a_readl(g, pgsp_falcon_debug1_r()); + data |= pgsp_falcon_debug1_ctxsw_mode_m(); + gk20a_writel(g, pgsp_falcon_debug1_r(), data); + + data = gk20a_readl(g, pgsp_falcon_engctl_r()); + data |= pgsp_falcon_engctl_switch_context_true_f(); + gk20a_writel(g, pgsp_falcon_engctl_r(), data); + + status = nvgpu_flcn_bl_bootstrap(&g->gsp_flcn, bl_info); + + return status; +} + +int gv100_gsp_setup_hw_and_bl_bootstrap(struct gk20a *g, + struct hs_acr *acr_desc, + struct nvgpu_falcon_bl_info *bl_info) +{ + u32 data = 0; + int err = 0; + + err = nvgpu_flcn_reset(&g->gsp_flcn); + if (err != 0) { + goto exit; + } + + data = gk20a_readl(g, pgsp_fbif_ctl_r()); + data |= pgsp_fbif_ctl_allow_phys_no_ctx_allow_f(); + gk20a_writel(g, pgsp_fbif_ctl_r(), data); + + /* setup apertures - virtual */ + gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), + pgsp_fbif_transcfg_mem_type_physical_f() | + pgsp_fbif_transcfg_target_local_fb_f()); + gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), + pgsp_fbif_transcfg_mem_type_virtual_f()); + /* setup apertures - physical */ + gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), + pgsp_fbif_transcfg_mem_type_physical_f() | + pgsp_fbif_transcfg_target_local_fb_f()); + gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), + pgsp_fbif_transcfg_mem_type_physical_f() | + pgsp_fbif_transcfg_target_coherent_sysmem_f()); + gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), + pgsp_fbif_transcfg_mem_type_physical_f() | + pgsp_fbif_transcfg_target_noncoherent_sysmem_f()); + + err = gsp_flcn_bl_bootstrap(g, bl_info); + +exit: + return err; +} diff --git a/drivers/gpu/nvgpu/gv100/gsp_gv100.h b/drivers/gpu/nvgpu/gv100/gsp_gv100.h index a4363d73..71d4564e 100644 --- a/drivers/gpu/nvgpu/gv100/gsp_gv100.h +++ b/drivers/gpu/nvgpu/gv100/gsp_gv100.h @@ -24,5 +24,8 @@ #define GSP_GV100_H int gv100_gsp_reset(struct gk20a *g); +int gv100_gsp_setup_hw_and_bl_bootstrap(struct gk20a *g, + struct hs_acr *acr_desc, + struct nvgpu_falcon_bl_info *bl_info); #endif /*GSP_GV100_H */ -- cgit v1.2.2