From 14949fbad615ef55adf08c39fd7614d1cbd4109e Mon Sep 17 00:00:00 2001 From: Tejal Kudav Date: Tue, 21 Aug 2018 13:14:26 +0530 Subject: gpu: nvgpu: Remove NVHSCLK coreclk programming top_nvhsclk_ctrl_e_clk_core and top_nvhsclk_ctrl_swap_clk_core default to values 1 and 0 respectively on reset. We need not explicitly program them to same values. JIRA NVGPU-966 Change-Id: I71976c73d74cf81184c79ac9a23e01d26c31be42 Signed-off-by: Tejal Kudav Reviewed-on: https://git-master.nvidia.com/r/1803639 Reviewed-by: svc-misra-checker GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/nvlink_gv100.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100') diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c index e32b303d..df948301 100644 --- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c +++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c @@ -1485,12 +1485,8 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask) reg = set_field(reg, top_nvhsclk_ctrl_e_clk_nvl_m(), top_nvhsclk_ctrl_e_clk_nvl_f(pad_ctrl)); - reg = set_field(reg, top_nvhsclk_ctrl_e_clk_core_m(), - top_nvhsclk_ctrl_e_clk_core_f(0x1)); reg = set_field(reg, top_nvhsclk_ctrl_swap_clk_nvl_m(), top_nvhsclk_ctrl_swap_clk_nvl_f(swap_ctrl)); - reg = set_field(reg, top_nvhsclk_ctrl_swap_clk_core_m(), - top_nvhsclk_ctrl_swap_clk_core_f(0x0)); gk20a_writel(g, top_nvhsclk_ctrl_r(), reg); -- cgit v1.2.2