From 744f7f049867c83ecb2c76681cb80ec789459491 Mon Sep 17 00:00:00 2001
From: Seema Khowala <seemaj@nvidia.com>
Date: Wed, 18 Apr 2018 16:18:59 -0700
Subject: gpu: nvgpu: add gr hal for fecs_ctxsw_mailbox size

fecs_ctxsw_mailbox_size varies per chip. Use hal to
get the size. Also dump fecs_ctxsw_status_1 to help
debug

Bug 2093809

Change-Id: I5a50281e9d78fe0e4a75d03971169e3e9679967a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1698026
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
---
 drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'drivers/gpu/nvgpu/gv100/hal_gv100.c')

diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index d972d4a5..fbf6e046 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -111,6 +111,7 @@
 #include <nvgpu/hw/gv100/hw_top_gv100.h>
 #include <nvgpu/hw/gv100/hw_pram_gv100.h>
 #include <nvgpu/hw/gv100/hw_pwr_gv100.h>
+#include <nvgpu/hw/gv100/hw_gr_gv100.h>
 
 static int gv100_get_litter_value(struct gk20a *g, int value)
 {
@@ -434,6 +435,7 @@ static const struct gpu_ops gv100_ops = {
 		.get_pmm_per_chiplet_offset =
 			gr_gv11b_get_pmm_per_chiplet_offset,
 		.split_fbpa_broadcast_addr = gr_gv100_split_fbpa_broadcast_addr,
+		.fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v,
 	},
 	.fb = {
 		.reset = gv100_fb_reset,
-- 
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