From ed8ac6e005d95e051bd03a182bbe0aa09a3c2266 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Mon, 16 Oct 2017 12:24:59 -0700 Subject: gpu: nvgpu: fix smid generation of perf tables SMID tables were generated according with the local tpc and the pagepool and cb buffers from a different chip and did not take performance in consideration, which made compute kernels hang with CTAs on the fly. This change ensures we are using the right sizes and adds proper enumeration of smids. JIRA: NVGPUGV100-36 bug 2004378 Change-Id: Ic8f50c325d6d6720cca41d9740ae4f5f51e1100a Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1581664 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/gr_gv100.h | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 drivers/gpu/nvgpu/gv100/gr_gv100.h (limited to 'drivers/gpu/nvgpu/gv100/gr_gv100.h') diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.h b/drivers/gpu/nvgpu/gv100/gr_gv100.h new file mode 100644 index 00000000..460b05ae --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.h @@ -0,0 +1,36 @@ +/* + * GV100 GPU GR + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NVGPU_GR_GV100_H_ +#define _NVGPU_GR_GV100_H_ + +void gr_gv100_bundle_cb_defaults(struct gk20a *g); +void gr_gv100_cb_size_default(struct gk20a *g); +void gr_gv100_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); +void gr_gv100_init_sm_id_table(struct gk20a *g); +void gr_gv100_program_sm_id_numbering(struct gk20a *g, + u32 gpc, u32 tpc, u32 smid); +int gr_gv100_load_smid_config(struct gk20a *g); + +#endif -- cgit v1.2.2 From 20294264468eecc8c1a065aa83d5f1b46ff07e7e Mon Sep 17 00:00:00 2001 From: David Nieto Date: Mon, 23 Oct 2017 14:01:28 -0700 Subject: gpu: nvgpu: gv1xx: resize patch buffer Follow the sizing consideration in bug 1753763 to support dynamic TPC modes and subcontexts. bug 200350539 Change-Id: Ibbdbf02f9c2ea3f082c1b2810ae7176b0775d461 Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1584034 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/gr_gv100.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv100/gr_gv100.h') diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.h b/drivers/gpu/nvgpu/gv100/gr_gv100.h index 460b05ae..612f76f9 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.h +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.h @@ -32,5 +32,5 @@ void gr_gv100_init_sm_id_table(struct gk20a *g); void gr_gv100_program_sm_id_numbering(struct gk20a *g, u32 gpc, u32 tpc, u32 smid); int gr_gv100_load_smid_config(struct gk20a *g); - +u32 gr_gv100_get_patch_slots(struct gk20a *g); #endif -- cgit v1.2.2