From 6b26d233499f9d447f06e8e72c72ed6728762e37 Mon Sep 17 00:00:00 2001 From: Srirangan Date: Thu, 2 Aug 2018 15:17:55 +0530 Subject: gpu: nvgpu: Fix MISRA 15.6 violations MISRA Rule-15.6 requires that all loop bodies must be enclosed in braces including single statement loop bodies. This patch fix the MISRA violations due to single statement loop bodies without braces by adding them. JIRA NVGPU-989 Change-Id: If79f56f92b94d0114477b66a6f654ac16ee8ea27 Signed-off-by: Srirangan Reviewed-on: https://git-master.nvidia.com/r/1791194 Reviewed-by: Adeel Raza GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/gr_gv100.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100/gr_gv100.c') diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c index 97affdd9..13092f2a 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c @@ -229,9 +229,11 @@ int gr_gv100_init_sm_id_table(struct gk20a *g) goto exit_build_table; } - for (gpc = 0; gpc < g->gr.gpc_count; gpc++) - for (pes = 0; pes < g->gr.gpc_ppc_count[gpc]; pes++) + for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { + for (pes = 0; pes < g->gr.gpc_ppc_count[gpc]; pes++) { gpc_tpc_mask[gpc] |= g->gr.pes_tpc_mask[pes][gpc]; + } + } for (gtpc = 0; gtpc < g->gr.tpc_count; gtpc++) { maxperf = -1; -- cgit v1.2.2