From de8e057f7eebcfe676278826ab457bf86b1b36fd Mon Sep 17 00:00:00 2001 From: David Nieto Date: Thu, 3 Aug 2017 21:43:50 -0700 Subject: gpu: nvgpu: GV100 support Adds support of GV100 up to devinit. JIRA: EVLR-1693 Change-Id: Ic7aa5f1c20714e05954139f143abb6a3459858fc Signed-off-by: David Nieto Reviewed-on: https://git-master.nvidia.com/r/1532747 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv100/fb_gv100.c | 58 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 drivers/gpu/nvgpu/gv100/fb_gv100.c (limited to 'drivers/gpu/nvgpu/gv100/fb_gv100.c') diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c new file mode 100644 index 00000000..a3785266 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c @@ -0,0 +1,58 @@ +/* + * GV100 FB + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include +#include +#include +#include + +#include "gk20a/gk20a.h" +#include "gv11b/fb_gv11b.h" +#include "gv100/fb_gv100.h" + +#include + +#define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */ +#define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */ + +static void gv100_fb_reset(struct gk20a *g) +{ + u32 val; + int retries = HW_SCRUB_TIMEOUT_MAX / HW_SCRUB_TIMEOUT_DEFAULT; + + nvgpu_info(g, "reset gv100 fb"); + + /* wait for memory to be accessible */ + do { + u32 w = gk20a_readl(g, fb_niso_scrub_status_r()); + if (fb_niso_scrub_status_flag_v(w)) { + nvgpu_info(g, "done"); + break; + } + nvgpu_udelay(HW_SCRUB_TIMEOUT_DEFAULT); + } while (--retries); + + val = gk20a_readl(g, fb_mmu_priv_level_mask_r()); + val &= ~fb_mmu_priv_level_mask_write_violation_m(); + gk20a_writel(g, fb_mmu_priv_level_mask_r(), val); +} + +void gv100_init_fb(struct gpu_ops *gops) +{ + gv11b_init_fb(gops); + gops->fb.reset = gv100_fb_reset; +} -- cgit v1.2.2 From 4bb0896912440d126ae47da350b448f37dabc63d Mon Sep 17 00:00:00 2001 From: Sunny He Date: Mon, 31 Jul 2017 14:40:46 -0700 Subject: gpu: nvgpu: Reorg fb HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the fb sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I3fdbf6059ef664caf8d33797a8a5f3f8eb6485bf Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1537748 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/fb_gv100.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100/fb_gv100.c') diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c index a3785266..319ebad6 100644 --- a/drivers/gpu/nvgpu/gv100/fb_gv100.c +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c @@ -21,7 +21,6 @@ #include #include "gk20a/gk20a.h" -#include "gv11b/fb_gv11b.h" #include "gv100/fb_gv100.h" #include @@ -29,7 +28,7 @@ #define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */ #define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */ -static void gv100_fb_reset(struct gk20a *g) +void gv100_fb_reset(struct gk20a *g) { u32 val; int retries = HW_SCRUB_TIMEOUT_MAX / HW_SCRUB_TIMEOUT_DEFAULT; @@ -50,9 +49,3 @@ static void gv100_fb_reset(struct gk20a *g) val &= ~fb_mmu_priv_level_mask_write_violation_m(); gk20a_writel(g, fb_mmu_priv_level_mask_r(), val); } - -void gv100_init_fb(struct gpu_ops *gops) -{ - gv11b_init_fb(gops); - gops->fb.reset = gv100_fb_reset; -} -- cgit v1.2.2 From d61643c0200983dc340d37962bb0a3ca900a3e97 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 25 Sep 2017 08:59:28 -0700 Subject: gpu: nvgpu: gv11b: Change license for common files to MIT Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity Reviewed-by: David Martinez Nieto Reviewed-by: Seshendra Gadagottu Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gv100/fb_gv100.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/nvgpu/gv100/fb_gv100.c') diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c index 319ebad6..bcb6d740 100644 --- a/drivers/gpu/nvgpu/gv100/fb_gv100.c +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c @@ -3,14 +3,23 @@ * * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include -- cgit v1.2.2 From 2904e3ac0081d4e898378f6ba667658c85547368 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 4 Oct 2017 19:41:04 +0530 Subject: gpu: nvgpu: gv100 memory unlock support - Added method to load mem unlock binary into nvdec falcon & execute to perform mem unlock if VPR enabled. - Updated .mem_unlock gv100 HAL to point method gv100_fb_memory_unlock(). - Updated .mem_unlock gv11b HAL to NULL. - Added vpr info hw registers - Added nvdec enable hw register Change-Id: Ia4bf820ae103baede679d300d1d390fd748c919a Signed-off-by: Mahantesh Kumbar (cherry picked from commit 2e176ad9d47316bf4d001692a2ae07e6c1fb1ccb) Reviewed-on: https://git-master.nvidia.com/r/1573101 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/fb_gv100.c | 124 +++++++++++++++++++++++++++++++++++++ 1 file changed, 124 insertions(+) (limited to 'drivers/gpu/nvgpu/gv100/fb_gv100.c') diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c index bcb6d740..0a2939bf 100644 --- a/drivers/gpu/nvgpu/gv100/fb_gv100.c +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c @@ -28,14 +28,25 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include #include "gk20a/gk20a.h" #include "gv100/fb_gv100.h" +#include "gm20b/acr_gm20b.h" #include +#include +#include #define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */ #define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */ +#define MEM_UNLOCK_TIMEOUT 3500 /* msec */ void gv100_fb_reset(struct gk20a *g) { @@ -58,3 +69,116 @@ void gv100_fb_reset(struct gk20a *g) val &= ~fb_mmu_priv_level_mask_write_violation_m(); gk20a_writel(g, fb_mmu_priv_level_mask_r(), val); } + +int gv100_fb_memory_unlock(struct gk20a *g) +{ + struct nvgpu_firmware *mem_unlock_fw = NULL; + struct bin_hdr *hsbin_hdr = NULL; + struct acr_fw_header *fw_hdr = NULL; + u32 *mem_unlock_ucode = NULL; + u32 *mem_unlock_ucode_header = NULL; + u32 sec_imem_dest = 0; + u32 val = 0; + int err = 0; + + nvgpu_log_fn(g, " "); + + /* Check vpr enable status */ + val = gk20a_readl(g, fb_mmu_vpr_info_r()); + val &= ~fb_mmu_vpr_info_index_m(); + val |= fb_mmu_vpr_info_index_cya_lo_v(); + gk20a_writel(g, fb_mmu_vpr_info_r(), val); + val = gk20a_readl(g, fb_mmu_vpr_info_r()); + if (!(val & fb_mmu_vpr_info_cya_lo_in_use_m())) { + nvgpu_log_info(g, "mem unlock not required on this SKU, skipping"); + goto exit; + } + + /* get mem unlock ucode binary */ + mem_unlock_fw = nvgpu_request_firmware(g, "mem_unlock.bin", 0); + if (!mem_unlock_fw) { + nvgpu_err(g, "mem unlock ucode get fail"); + err = -ENOENT; + goto exit; + } + + /* Enable nvdec */ + g->ops.mc.enable(g, mc_enable_nvdec_enabled_f()); + + /* nvdec falcon reset */ + nvgpu_flcn_reset(&g->nvdec_flcn); + + hsbin_hdr = (struct bin_hdr *)mem_unlock_fw->data; + fw_hdr = (struct acr_fw_header *)(mem_unlock_fw->data + + hsbin_hdr->header_offset); + + mem_unlock_ucode_header = (u32 *)(mem_unlock_fw->data + + fw_hdr->hdr_offset); + mem_unlock_ucode = (u32 *)(mem_unlock_fw->data + + hsbin_hdr->data_offset); + + /* Patch Ucode singnatures */ + if (acr_ucode_patch_sig(g, mem_unlock_ucode, + (u32 *)(mem_unlock_fw->data + fw_hdr->sig_prod_offset), + (u32 *)(mem_unlock_fw->data + fw_hdr->sig_dbg_offset), + (u32 *)(mem_unlock_fw->data + fw_hdr->patch_loc), + (u32 *)(mem_unlock_fw->data + fw_hdr->patch_sig)) < 0) { + nvgpu_err(g, "mem unlock patch signatures fail"); + err = -EPERM; + goto exit; + } + + /* Clear interrupts */ + nvgpu_flcn_set_irq(&g->nvdec_flcn, false, 0x0, 0x0); + + /* Copy Non Secure IMEM code */ + nvgpu_flcn_copy_to_imem(&g->nvdec_flcn, 0, + (u8 *)&mem_unlock_ucode[ + mem_unlock_ucode_header[OS_CODE_OFFSET] >> 2], + mem_unlock_ucode_header[OS_CODE_SIZE], 0, false, + GET_IMEM_TAG(mem_unlock_ucode_header[OS_CODE_OFFSET])); + + /* Put secure code after non-secure block */ + sec_imem_dest = GET_NEXT_BLOCK(mem_unlock_ucode_header[OS_CODE_SIZE]); + + nvgpu_flcn_copy_to_imem(&g->nvdec_flcn, sec_imem_dest, + (u8 *)&mem_unlock_ucode[ + mem_unlock_ucode_header[APP_0_CODE_OFFSET] >> 2], + mem_unlock_ucode_header[APP_0_CODE_SIZE], 0, true, + GET_IMEM_TAG(mem_unlock_ucode_header[APP_0_CODE_OFFSET])); + + /* load DMEM: ensure that signatures are patched */ + nvgpu_flcn_copy_to_dmem(&g->nvdec_flcn, 0, (u8 *)&mem_unlock_ucode[ + mem_unlock_ucode_header[OS_DATA_OFFSET] >> 2], + mem_unlock_ucode_header[OS_DATA_SIZE], 0); + + nvgpu_log_info(g, "nvdec sctl reg %x\n", + gk20a_readl(g, g->nvdec_flcn.flcn_base + + falcon_falcon_sctl_r())); + + /* set BOOTVEC to start of non-secure code */ + nvgpu_flcn_bootstrap(&g->nvdec_flcn, 0); + + /* wait for complete & halt */ + nvgpu_flcn_wait_for_halt(&g->nvdec_flcn, MEM_UNLOCK_TIMEOUT); + + /* check mem unlock status */ + val = nvgpu_flcn_mailbox_read(&g->nvdec_flcn, 0); + if (val) { + nvgpu_err(g, "memory unlock failed, err %x", val); + err = -1; + goto exit; + } + + nvgpu_log_info(g, "nvdec sctl reg %x\n", + gk20a_readl(g, g->nvdec_flcn.flcn_base + + falcon_falcon_sctl_r())); + +exit: + if (mem_unlock_fw) + nvgpu_release_firmware(g, mem_unlock_fw); + + nvgpu_log_fn(g, "done, status - %d", err); + + return err; +} -- cgit v1.2.2