From 180604fec0bde1710923e78a3877d49892cbf883 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Fri, 26 Jan 2018 17:56:55 -0800 Subject: gpu: nvgpu: gv100: fb hal to init and enable nvlink Add the following hals: (1) init_nvlink to configure nvlink(s) for sysmem in HSHUB (2) enable_nvlink to switch from PCIe sysmem to nvlink sysmem, and setup atomics. Change-Id: I73d2370aaf8e0530158a1091d9efef4a8cf2aac5 Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/1648044 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/fb_gv100.c | 52 +++++++++++++++++++++++++++++++++++++- 1 file changed, 51 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gv100/fb_gv100.c') diff --git a/drivers/gpu/nvgpu/gv100/fb_gv100.c b/drivers/gpu/nvgpu/gv100/fb_gv100.c index 0a2939bf..84a8d64a 100644 --- a/drivers/gpu/nvgpu/gv100/fb_gv100.c +++ b/drivers/gpu/nvgpu/gv100/fb_gv100.c @@ -1,7 +1,7 @@ /* * GV100 FB * - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -182,3 +182,53 @@ exit: return err; } + +int gv100_fb_init_nvlink(struct gk20a *g) +{ + u32 data; + u32 mask = g->nvlink.enabled_links; + + /* Map enabled link to SYSMEM */ + data = nvgpu_readl(g, fb_hshub_config0_r()); + data = set_field(data, fb_hshub_config0_sysmem_nvlink_mask_m(), + fb_hshub_config0_sysmem_nvlink_mask_f(mask)); + nvgpu_writel(g, fb_hshub_config0_r(), data); + + return 0; +} + +int gv100_fb_enable_nvlink(struct gk20a *g) +{ + u32 data; + + nvgpu_log(g, gpu_dbg_nvlink|gpu_dbg_info, "enabling nvlink"); + + /* Enable nvlink for NISO FBHUB */ + data = nvgpu_readl(g, fb_niso_cfg1_r()); + data = set_field(data, fb_niso_cfg1_sysmem_nvlink_m(), + fb_niso_cfg1_sysmem_nvlink_enabled_f()); + nvgpu_writel(g, fb_niso_cfg1_r(), data); + + /* Setup atomics */ + data = nvgpu_readl(g, fb_mmu_ctrl_r()); + data = set_field(data, fb_mmu_ctrl_atomic_capability_mode_m(), + fb_mmu_ctrl_atomic_capability_mode_rmw_f()); + nvgpu_writel(g, fb_mmu_ctrl_r(), data); + + data = nvgpu_readl(g, fb_hsmmu_pri_mmu_ctrl_r()); + data = set_field(data, fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_m(), + fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_f()); + nvgpu_writel(g, fb_hsmmu_pri_mmu_ctrl_r(), data); + + data = nvgpu_readl(g, fb_fbhub_num_active_ltcs_r()); + data = set_field(data, fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(), + fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f()); + nvgpu_writel(g, fb_fbhub_num_active_ltcs_r(), data); + + data = nvgpu_readl(g, fb_hshub_num_active_ltcs_r()); + data = set_field(data, fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(), + fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f()); + nvgpu_writel(g, fb_hshub_num_active_ltcs_r(), data); + + return 0; +} -- cgit v1.2.2