From 850f2ad8ada4f4c2c753644f387d75e6d75ac28b Mon Sep 17 00:00:00 2001 From: absalam Date: Thu, 20 Sep 2018 12:21:33 +0530 Subject: gpu: nvgpu:Add sysfs node for GV100 clocks Creates sysfs nodes to read clk freq on GV100 Following sysfs nodes are created: gpcclk,xbarclk,sysclk Uses default clock source and counters for measurement Bug 200446261 Change-Id: I6903ba77fbe34e3f486f4b663e70eab4e7c5d662 Signed-off-by: absalam Reviewed-on: https://git-master.nvidia.com/r/1828030 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/clk_gv100.h | 63 +++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 drivers/gpu/nvgpu/gv100/clk_gv100.h (limited to 'drivers/gpu/nvgpu/gv100/clk_gv100.h') diff --git a/drivers/gpu/nvgpu/gv100/clk_gv100.h b/drivers/gpu/nvgpu/gv100/clk_gv100.h new file mode 100644 index 00000000..d3356a7f --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/clk_gv100.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef CLK_GV100_H +#define CLK_GV100_H + +#include +#include "gk20a/gk20a.h" + +#define CLK_NAMEMAP_INDEX_GPCCLK 0x00 +#define CLK_NAMEMAP_INDEX_XBARCLK 0x02 +#define CLK_NAMEMAP_INDEX_SYSCLK 0x07 /* SYSPLL */ +#define CLK_NAMEMAP_INDEX_DRAMCLK 0x20 /* DRAMPLL */ + +#define CLK_DEFAULT_CNTRL_SETTLE_RETRIES 10 +#define CLK_DEFAULT_CNTRL_SETTLE_USECS 5 +#define CLK_MAX_CNTRL_REGISTERS 2 + +#define XTAL_CNTR_CLKS 27000 /* 1000usec at 27KHz XTAL */ +#define XTAL_CNTR_DELAY 10000 /* we need acuracy up to the 10ms */ +#define XTAL_SCALE_TO_KHZ 1 +#define NUM_NAMEMAPS (3U) +#define XTAL4X_KHZ 108000 + +u32 gv100_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c); +struct namemap_cfg { + u32 namemap; + u32 is_enable; /* Namemap enabled */ + u32 is_counter; /* Using cntr */ + struct gk20a *g; + struct { + u32 reg_ctrl_addr; + u32 reg_ctrl_idx; + u32 reg_cntr_addr[CLK_MAX_CNTRL_REGISTERS]; + } cntr; + u32 scale; + char name[24]; +}; + +int gv100_init_clk_support(struct gk20a *g); +u32 gv100_crystal_clk_hz(struct gk20a *g); +unsigned long gv100_clk_measure_freq(struct gk20a *g, u32 api_domain); +int gv100_suspend_clk_support(struct gk20a *g); + +#endif /* CLK_GV100_H */ -- cgit v1.2.2