From ef69df6dae3dd21f10b035e687381a578344e417 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 14 Feb 2019 13:36:19 -0800 Subject: gpu: nvgpu: add hal to mask/unmask intr during teardown ctxsw timeout error prevents recovery as it can get triggered periodically. Disable ctxsw timeout interrupt to allow recovery. Bug 2092051 Bug 2429295 Bug 2484211 Bug 1890287 Change-Id: I47470e13968d8b26cdaf519b62fd510bc7ea05d9 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/2019645 Signed-off-by: Debarshi Dutta (cherry picked from commit 68c13e2f0447118d7391807c9b9269749d09a4ec in dev-kernel) Reviewed-on: https://git-master.nvidia.com/r/2024899 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index b3379253..5fcfb32f 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -488,6 +488,8 @@ static const struct gpu_ops gp10b_ops = { .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs, .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, + .teardown_mask_intr = gk20a_fifo_teardown_mask_intr, + .teardown_unmask_intr = gk20a_fifo_teardown_unmask_intr, .handle_sched_error = gk20a_fifo_handle_sched_error, .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, -- cgit v1.2.2