From dc281d6a9ebadaeb66dab092b40b7d6f4559ee39 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Tue, 30 Apr 2019 17:19:51 -0700 Subject: gpu: nvgpu: add SET_CTX_MMU_DEBUG_MODE ioctl Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU debug mode for a given context. Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL for a given channel. HAL implementation for native case is gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly writes to the register if the context is resident, or writes to gr context otherwise. Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature. NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode, so the feature is only enabled on TU104 for now. Bug 2515097 But 2713590 Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/2110720 (cherry-picked from commit af2ccb811d3de06f052b1dee39bd9ffa863ac8ce) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208767 Reviewed-by: Kajetan Dutka Reviewed-by: Alex Waterman Reviewed-by: Winnie Hsu Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: Kajetan Dutka Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 561d24d8..eea40d5e 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B Tegra HAL interface * - * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -295,6 +295,7 @@ static const struct gpu_ops gp10b_ops = { .get_lrf_tex_ltc_dram_override = get_ecc_override_val, .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, + .set_mmu_debug_mode = NULL, .record_sm_error_state = gm20b_gr_record_sm_error_state, .clear_sm_error_state = gm20b_gr_clear_sm_error_state, .suspend_contexts = gr_gp10b_suspend_contexts, @@ -783,6 +784,7 @@ int gp10b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false); __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); + __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ if (gops->fuse.check_priv_security(g)) { -- cgit v1.2.2