From d3415f27c465b057a828c51dba7d8c1f70f4d289 Mon Sep 17 00:00:00 2001 From: Lauri Peltonen Date: Mon, 10 Jul 2017 15:00:50 +0300 Subject: gpu: nvgu: Support SET_BES_CROP_DEBUG3 sw method The new SET_BES_CROP_DEBUG3 sw method is used to flip two fields in the NV_PGRAPH_PRI_BES_CROP_DEBUG3 register. The sw method is used by the user space driver to disable enough ROP optimizations to maintain ZBC state of target tiles. Bug 1942454 Change-Id: Id4e4d9d06c6c66080d06b6d4694546fe5cba8436 Signed-off-by: Lauri Peltonen Reviewed-on: https://git-master.nvidia.com/r/1516202 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 29 +++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 1 + 2 files changed, 30 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index d9d045bd..6ef27abf 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -642,6 +642,31 @@ static void gr_gp10b_set_coalesce_buffer_size(struct gk20a *g, u32 data) gk20a_dbg_fn("done"); } +static void gr_gp10b_set_bes_crop_debug3(struct gk20a *g, u32 data) +{ + u32 val; + + gk20a_dbg_fn(""); + + val = gk20a_readl(g, gr_bes_crop_debug3_r()); + if ((data & 1)) { + val = set_field(val, + gr_bes_crop_debug3_blendopt_read_suppress_m(), + gr_bes_crop_debug3_blendopt_read_suppress_enabled_f()); + val = set_field(val, + gr_bes_crop_debug3_blendopt_fill_override_m(), + gr_bes_crop_debug3_blendopt_fill_override_enabled_f()); + } else { + val = set_field(val, + gr_bes_crop_debug3_blendopt_read_suppress_m(), + gr_bes_crop_debug3_blendopt_read_suppress_disabled_f()); + val = set_field(val, + gr_bes_crop_debug3_blendopt_fill_override_m(), + gr_bes_crop_debug3_blendopt_fill_override_disabled_f()); + } + gk20a_writel(g, gr_bes_crop_debug3_r(), val); +} + static int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr, u32 class_num, u32 offset, u32 data) { @@ -680,6 +705,9 @@ static int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr, case NVC097_SET_RD_COALESCE: gr_gm20b_set_rd_coalesce(g, data); break; + case NVC097_SET_BES_CROP_DEBUG3: + g->ops.gr.set_bes_crop_debug3(g, data); + break; default: goto fail; } @@ -2364,6 +2392,7 @@ void gp10b_init_gr(struct gpu_ops *gops) gr_gp10b_set_alpha_circular_buffer_size; gops->gr.set_circular_buffer_size = gr_gp10b_set_circular_buffer_size; + gops->gr.set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3; gops->gr.init_ctx_state = gr_gp10b_init_ctx_state; gops->gr.alloc_gr_ctx = gr_gp10b_alloc_gr_ctx; gops->gr.free_gr_ctx = gr_gp10b_free_gr_ctx; diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index 76e48075..aac9eb65 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -37,6 +37,7 @@ enum { #define NVC097_SET_RD_COALESCE 0x102c #define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280 #define NVC097_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC097_SET_BES_CROP_DEBUG3 0x10c4 #define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528 #define NVC0C0_SET_RD_COALESCE 0x0228 -- cgit v1.2.2