From c9665079d7b12f22a847c62587724b4ee120ca6e Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Tue, 21 Mar 2017 12:55:35 -0700 Subject: gpu: nvgpu: rename mem_desc to nvgpu_mem Renaming was done with the following command: $ find -type f | \ xargs sed -i 's/struct mem_desc/struct nvgpu_mem/g' Also rename mem_desc.[ch] to nvgpu_mem.[ch]. JIRA NVGPU-12 Change-Id: I69395758c22a56aa01e3dffbcded70a729bf559a Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/1325547 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 4 ++-- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 12 ++++++------ drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 10 +++++----- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 8 ++++---- 4 files changed, 17 insertions(+), 17 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b') diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index 3787662b..a7e77232 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c @@ -27,7 +27,7 @@ #include static void gp10b_set_pdb_fault_replay_flags(struct gk20a *g, - struct mem_desc *mem) + struct nvgpu_mem *mem) { u32 val; @@ -83,7 +83,7 @@ static int channel_gp10b_setup_ramfc(struct channel_gk20a *c, unsigned long acquire_timeout, u32 flags) { struct gk20a *g = c->g; - struct mem_desc *mem = &c->inst_block; + struct nvgpu_mem *mem = &c->inst_block; gk20a_dbg_fn(""); diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index fc831e75..8e1517f6 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -832,7 +832,7 @@ static int gr_gp10b_init_ctx_state(struct gk20a *g) } int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size, - struct mem_desc *mem) + struct nvgpu_mem *mem) { int err; @@ -1037,7 +1037,7 @@ fail_free_gk20a_ctx: static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm, struct gr_ctx_desc *gr_ctx) { - struct mem_desc *mem = &gr_ctx->mem; + struct nvgpu_mem *mem = &gr_ctx->mem; if (nvgpu_mem_begin(g, mem)) { WARN_ON("Cannot map context"); @@ -1108,7 +1108,7 @@ static void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx, - struct mem_desc *mem) + struct nvgpu_mem *mem) { struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; u32 gfxp_preempt_option = @@ -2072,7 +2072,7 @@ static int gr_gp10b_set_boosted_ctx(struct channel_gk20a *ch, { struct gr_ctx_desc *gr_ctx = ch->ch_ctx.gr_ctx; struct gk20a *g = ch->g; - struct mem_desc *mem = &gr_ctx->mem; + struct nvgpu_mem *mem = &gr_ctx->mem; int err = 0; gr_ctx->boosted_ctx = boost; @@ -2101,7 +2101,7 @@ unmap_ctx: return err; } -static void gr_gp10b_update_boosted_ctx(struct gk20a *g, struct mem_desc *mem, +static void gr_gp10b_update_boosted_ctx(struct gk20a *g, struct nvgpu_mem *mem, struct gr_ctx_desc *gr_ctx) { u32 v; @@ -2119,7 +2119,7 @@ static int gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, struct gk20a *g = ch->g; struct tsg_gk20a *tsg; struct vm_gk20a *vm; - struct mem_desc *mem = &gr_ctx->mem; + struct nvgpu_mem *mem = &gr_ctx->mem; u32 class; int err = 0; diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index ffb15d91..c4c206c3 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -42,7 +42,7 @@ enum { void gp10b_init_gr(struct gpu_ops *ops); int gr_gp10b_init_fs_state(struct gk20a *g); int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size, - struct mem_desc *mem); + struct nvgpu_mem *mem); void gr_gp10b_create_sysfs(struct device *dev); struct ecc_stat { @@ -95,10 +95,10 @@ struct gr_t18x { }; struct gr_ctx_desc_t18x { - struct mem_desc preempt_ctxsw_buffer; - struct mem_desc spill_ctxsw_buffer; - struct mem_desc betacb_ctxsw_buffer; - struct mem_desc pagepool_ctxsw_buffer; + struct nvgpu_mem preempt_ctxsw_buffer; + struct nvgpu_mem spill_ctxsw_buffer; + struct nvgpu_mem betacb_ctxsw_buffer; + struct nvgpu_mem pagepool_ctxsw_buffer; u32 ctx_id; bool ctx_id_valid; bool cilp_preempt_pending; diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 8c6340f0..a0dc8c55 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -34,7 +34,7 @@ static u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) static int gp10b_init_mm_setup_hw(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; - struct mem_desc *inst_block = &mm->bar1.inst_block; + struct nvgpu_mem *inst_block = &mm->bar1.inst_block; int err = 0; gk20a_dbg_fn(""); @@ -68,7 +68,7 @@ static int gb10b_init_bar2_vm(struct gk20a *g) int err; struct mm_gk20a *mm = &g->mm; struct vm_gk20a *vm = &mm->bar2.vm; - struct mem_desc *inst_block = &mm->bar2.inst_block; + struct nvgpu_mem *inst_block = &mm->bar2.inst_block; u32 big_page_size = gk20a_get_platform(g->dev)->default_big_page_size; /* BAR2 aperture size is 32MB */ @@ -96,7 +96,7 @@ clean_up_va: static int gb10b_init_bar2_mm_hw_setup(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; - struct mem_desc *inst_block = &mm->bar2.inst_block; + struct nvgpu_mem *inst_block = &mm->bar2.inst_block; u64 inst_pa = gk20a_mm_inst_block_addr(g, inst_block); gk20a_dbg_fn(""); @@ -375,7 +375,7 @@ static const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, return gp10b_mm_levels; } -static void gp10b_mm_init_pdb(struct gk20a *g, struct mem_desc *inst_block, +static void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, struct vm_gk20a *vm) { u64 pdb_addr = gk20a_mem_get_base_addr(g, &vm->pdb.mem, 0); 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