From ac98827c9d81746020dce689f9eb8c4018a8c148 Mon Sep 17 00:00:00 2001 From: Vinod G Date: Tue, 26 Jun 2018 18:09:57 -0700 Subject: gpu: nvgpu: Add L2 register read-backs following writes LTC register write is followed by a register read and if data doesn't match code will report the error. Renamed existing nvgpu_writel_check function as nvgpu_writel_loop as it loops until the write get success. nvgpu_writel_check function write and read back and compare the data. Bug 2039150 Change-Id: I0a49be36aad23936f2d58aa82872710827da1d32 Signed-off-by: Vinod G Reviewed-on: https://git-master.nvidia.com/r/1762344 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 10 +++++----- drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 19 ++++++++++--------- 2 files changed, 15 insertions(+), 14 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 6249992a..424c8490 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -537,18 +537,18 @@ int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, gr->zbc_col_tbl[index].format = color_val->format; gr->zbc_col_tbl[index].ref_cnt++; - gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_r_r(index), + nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_r_r(index), color_val->color_ds[0]); - gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_g_r(index), + nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_g_r(index), color_val->color_ds[1]); - gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_b_r(index), + nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_b_r(index), color_val->color_ds[2]); - gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), + nvgpu_writel_loop(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), color_val->color_ds[3]); zbc_c = gk20a_readl(g, zbc_c_format_reg + (index & ~3)); zbc_c &= ~(0x7f << ((index % 4) * 7)); zbc_c |= color_val->format << ((index % 4) * 7); - gk20a_writel_check(g, zbc_c_format_reg + (index & ~3), zbc_c); + nvgpu_writel_loop(g, zbc_c_format_reg + (index & ~3), zbc_c); return 0; } diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index b0938f75..1e5807d5 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -156,14 +156,16 @@ int gp10b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, nvgpu_log_info(g, "clearing CBC lines %u..%u", min, iter_max); if (op == gk20a_cbc_op_clear) { - gk20a_writel( + nvgpu_writel_check( g, ltc_ltcs_ltss_cbc_ctrl2_r(), ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f( min)); - gk20a_writel( + + nvgpu_writel_check( g, ltc_ltcs_ltss_cbc_ctrl3_r(), ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f( iter_max)); + hw_op = ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(); full_cache_op = false; } else if (op == gk20a_cbc_op_clean) { @@ -251,10 +253,9 @@ void gp10b_ltc_isr(struct gk20a *g) ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val); ecc_stats_reg_val &= ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m()); - gk20a_writel(g, + nvgpu_writel_check(g, ltc_ltc0_lts0_dstg_ecc_report_r() + offset, ecc_stats_reg_val); - g->ops.mm.l2_flush(g, true); } if (ltc_intr & @@ -271,16 +272,16 @@ void gp10b_ltc_isr(struct gk20a *g) ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val); ecc_stats_reg_val &= ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m()); - gk20a_writel(g, + nvgpu_writel_check(g, ltc_ltc0_lts0_dstg_ecc_report_r() + offset, ecc_stats_reg_val); } nvgpu_err(g, "ltc%d, slice %d: %08x", ltc, slice, ltc_intr); - gk20a_writel(g, ltc_ltc0_lts0_intr_r() + - ltc_stride * ltc + lts_stride * slice, - ltc_intr); + nvgpu_writel_check(g, ltc_ltc0_lts0_intr_r() + + ltc_stride * ltc + lts_stride * slice, + ltc_intr); } } } @@ -314,5 +315,5 @@ void gp10b_ltc_set_enabled(struct gk20a *g, bool enabled) /* bypass enabled (no caching) */ reg |= reg_f; - gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); + nvgpu_writel_check(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); } -- cgit v1.2.2