From aa7ee8dac0cb29ee3244c7eef77eac8e7fc34dba Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 27 Mar 2018 11:52:27 -0700 Subject: gpu: nvgpu: enhance pbus error reporting -Dump timeout save0 and save1 even if they could be unreliable when fecs_tgt in set in save0 . This is good to have for debug purposes. -Add priv_ring hal for decode_error_code -Decode fecs error code for supported error types Bug 1998067 Change-Id: I60cb6902d099df4a7df45fa624e44d9e0d46360f Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1683014 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 + drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c | 9 ++++++--- drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h | 4 +++- 3 files changed, 10 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index dd413c5a..a6a66f93 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -646,6 +646,7 @@ static const struct gpu_ops gp10b_ops = { }, .priv_ring = { .isr = gp10b_priv_ring_isr, + .decode_error_code = gp10b_priv_ring_decode_error_code, }, .fuse = { .check_priv_security = gp10b_fuse_check_priv_security, diff --git a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c index 0fac76f2..12cd2a84 100644 --- a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c @@ -64,7 +64,7 @@ static const char *const error_type_badf5xyy[] = { "pri route error" }; -static void gp10b_priv_ring_decode_error_code(struct gk20a *g, +void gp10b_priv_ring_decode_error_code(struct gk20a *g, u32 error_code) { u32 error_type, error_type_index; @@ -141,7 +141,8 @@ void gp10b_priv_ring_isr(struct gk20a *g) pri_ringstation_sys_priv_error_info_subid_v(error_info), pri_ringstation_sys_priv_error_info_priv_level_v(error_info), error_code); - gp10b_priv_ring_decode_error_code(g, error_code); + if (g->ops.priv_ring.decode_error_code) + g->ops.priv_ring.decode_error_code(g, error_code); } if (status1) { @@ -166,7 +167,9 @@ void gp10b_priv_ring_isr(struct gk20a *g) pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(error_info), error_code); - gp10b_priv_ring_decode_error_code(g, error_code); + if (g->ops.priv_ring.decode_error_code) + g->ops.priv_ring.decode_error_code(g, + error_code); status1 = status1 & (~(BIT(gpc))); if (!status1) diff --git a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h index 5b004a58..dd418e5b 100644 --- a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h @@ -1,7 +1,7 @@ /* * GP10B PRIV ringmaster * - * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -27,5 +27,7 @@ struct gk20a; void gp10b_priv_ring_isr(struct gk20a *g); +void gp10b_priv_ring_decode_error_code(struct gk20a *g, + u32 error_code); #endif /*__PRIV_RING_GP10B_H__*/ -- cgit v1.2.2