From 959c02d6757c3c40748f7d2db1515885a5066a12 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Mon, 31 Jul 2017 18:54:38 -0700 Subject: gpu: nvgpu: Reorg mm HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ieb87a62f047510e51c52e6563d8e3fd5a65b5f28 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1537753 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 29 +++++++++++++++++++++++++++-- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 30 ++++++++---------------------- drivers/gpu/nvgpu/gp10b/mm_gp10b.h | 19 ++++++++++++++++--- 3 files changed, 51 insertions(+), 27 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index b0871155..a37295bb 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -17,6 +17,7 @@ #include "gk20a/fifo_gk20a.h" #include "gk20a/ctxsw_trace_gk20a.h" #include "gk20a/fecs_trace_gk20a.h" +#include "gk20a/mm_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/bus_gk20a.h" @@ -47,8 +48,8 @@ #include "gm20b/fifo_gm20b.h" #include "gm20b/pmu_gm20b.h" #include "gm20b/clk_gm20b.h" -#include "gm20b/fifo_gm20b.h" #include "gm20b/fb_gm20b.h" +#include "gm20b/mm_gm20b.h" #include "gp10b.h" #include "hal_gp10b.h" @@ -319,6 +320,30 @@ static const struct gpu_ops gp10b_ops = { .max_entries = gk20a_gr_max_entries, }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ + .mm = { + .support_sparse = gm20b_mm_support_sparse, + .gmmu_map = gk20a_locked_gmmu_map, + .gmmu_unmap = gk20a_locked_gmmu_unmap, + .vm_bind_channel = gk20a_vm_bind_channel, + .fb_flush = gk20a_mm_fb_flush, + .l2_invalidate = gk20a_mm_l2_invalidate, + .l2_flush = gk20a_mm_l2_flush, + .cbc_clean = gk20a_mm_cbc_clean, + .set_big_page_size = gm20b_mm_set_big_page_size, + .get_big_page_sizes = gm20b_mm_get_big_page_sizes, + .get_default_big_page_size = gp10b_mm_get_default_big_page_size, + .gpu_phys_addr = gm20b_gpu_phys_addr, + .get_physical_addr_bits = gp10b_mm_get_physical_addr_bits, + .get_mmu_levels = gp10b_mm_get_mmu_levels, + .init_pdb = gp10b_mm_init_pdb, + .init_mm_setup_hw = gp10b_init_mm_setup_hw, + .is_bar1_supported = gm20b_mm_is_bar1_supported, + .init_inst_block = gk20a_init_inst_block, + .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, + .init_bar2_vm = gb10b_init_bar2_vm, + .init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup, + .remove_bar2_vm = gp10b_remove_bar2_vm, + }, .pramin = { .enter = gk20a_pramin_enter, .exit = gk20a_pramin_exit, @@ -427,6 +452,7 @@ int gp10b_init_hal(struct gk20a *g) gops->fifo = gp10b_ops.fifo; gops->gr_ctx = gp10b_ops.gr_ctx; gops->fecs_trace = gp10b_ops.fecs_trace; + gops->mm = gp10b_ops.mm; gops->pramin = gp10b_ops.pramin; gops->therm = gp10b_ops.therm; gops->regops = gp10b_ops.regops; @@ -489,7 +515,6 @@ int gp10b_init_hal(struct gk20a *g) g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; gp10b_init_gr(g); - gp10b_init_mm(gops); gp10b_init_pmu_ops(g); gp10b_init_uncompressed_kind_map(); diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 9aa72e64..6b629ecf 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -27,17 +27,17 @@ #include #include -static u32 gp10b_mm_get_default_big_page_size(void) +u32 gp10b_mm_get_default_big_page_size(void) { return SZ_64K; } -static u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) +u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) { return 36; } -static int gp10b_init_mm_setup_hw(struct gk20a *g) +int gp10b_init_mm_setup_hw(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; struct nvgpu_mem *inst_block = &mm->bar1.inst_block; @@ -68,7 +68,7 @@ static int gp10b_init_mm_setup_hw(struct gk20a *g) } -static int gb10b_init_bar2_vm(struct gk20a *g) +int gb10b_init_bar2_vm(struct gk20a *g) { int err; struct mm_gk20a *mm = &g->mm; @@ -99,7 +99,7 @@ clean_up_va: return err; } -static int gb10b_init_bar2_mm_hw_setup(struct gk20a *g) +int gb10b_init_bar2_mm_hw_setup(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; struct nvgpu_mem *inst_block = &mm->bar2.inst_block; @@ -333,13 +333,13 @@ static const struct gk20a_mmu_level gp10b_mm_levels[] = { {.update_entry = NULL} }; -static const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, +const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, u32 big_page_size) { return gp10b_mm_levels; } -static void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, +void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, struct vm_gk20a *vm) { u64 pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem); @@ -360,7 +360,7 @@ static void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, ram_in_page_dir_base_hi_f(pdb_addr_hi)); } -static void gp10b_remove_bar2_vm(struct gk20a *g) +void gp10b_remove_bar2_vm(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; @@ -368,17 +368,3 @@ static void gp10b_remove_bar2_vm(struct gk20a *g) gk20a_free_inst_block(g, &mm->bar2.inst_block); nvgpu_vm_put(mm->bar2.vm); } - - -void gp10b_init_mm(struct gpu_ops *gops) -{ - gm20b_init_mm(gops); - gops->mm.get_default_big_page_size = gp10b_mm_get_default_big_page_size; - gops->mm.get_physical_addr_bits = gp10b_mm_get_physical_addr_bits; - gops->mm.init_mm_setup_hw = gp10b_init_mm_setup_hw; - gops->mm.init_bar2_vm = gb10b_init_bar2_vm; - gops->mm.init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup; - gops->mm.get_mmu_levels = gp10b_mm_get_mmu_levels; - gops->mm.init_pdb = gp10b_mm_init_pdb; - gops->mm.remove_bar2_vm = gp10b_remove_bar2_vm; -} diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h index 4cc71ea6..a0b9acd6 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,7 +14,20 @@ #ifndef MM_GP10B_H #define MM_GP10B_H -struct gpu_ops; +struct gk20a; +struct gk20a_mmu_level; +struct nvgpu_mem; +struct vm_gk20a; + +u32 gp10b_mm_get_default_big_page_size(void); +u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g); +int gp10b_init_mm_setup_hw(struct gk20a *g); +int gb10b_init_bar2_vm(struct gk20a *g); +int gb10b_init_bar2_mm_hw_setup(struct gk20a *g); +const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, + u32 big_page_size); +void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, + struct vm_gk20a *vm); +void gp10b_remove_bar2_vm(struct gk20a *g); -void gp10b_init_mm(struct gpu_ops *gops); #endif -- cgit v1.2.2