From 6b26d233499f9d447f06e8e72c72ed6728762e37 Mon Sep 17 00:00:00 2001 From: Srirangan Date: Thu, 2 Aug 2018 15:17:55 +0530 Subject: gpu: nvgpu: Fix MISRA 15.6 violations MISRA Rule-15.6 requires that all loop bodies must be enclosed in braces including single statement loop bodies. This patch fix the MISRA violations due to single statement loop bodies without braces by adding them. JIRA NVGPU-989 Change-Id: If79f56f92b94d0114477b66a6f654ac16ee8ea27 Signed-off-by: Srirangan Reviewed-on: https://git-master.nvidia.com/r/1791194 Reviewed-by: Adeel Raza GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 3 ++- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 7792728c..5a22af80 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1572,8 +1572,9 @@ int gr_gp10b_load_smid_config(struct gk20a *g) gk20a_writel(g, gr_cwd_gpc_tpc_id_r(i), reg); } - for (i = 0; i < gr_cwd_sm_id__size_1_v(); i++) + for (i = 0; i < gr_cwd_sm_id__size_1_v(); i++) { gk20a_writel(g, gr_cwd_sm_id_r(i), tpc_sm_id[i]); + } nvgpu_kfree(g, tpc_sm_id); diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index a0e08437..7036ca15 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -286,8 +286,9 @@ static enum gmmu_pgsz_gk20a gp10b_get_pde0_pgsz(struct gk20a *g, if (!pd->mem) return pgsz; - for (i = 0; i < GP10B_PDE0_ENTRY_SIZE >> 2; i++) + for (i = 0; i < GP10B_PDE0_ENTRY_SIZE >> 2; i++) { pde_v[i] = nvgpu_mem_rd32(g, pd->mem, pde_offset + i); + } /* * Check if the aperture AND address are set -- cgit v1.2.2