From 39a9e251da0fb4da8512593d3ce4f6eba47d5e0c Mon Sep 17 00:00:00 2001 From: Peter Boonstoppel Date: Tue, 2 May 2017 12:09:40 -0700 Subject: gpu: nvgpu: Add czf_bypass sysfs node for gp10b This change adds a new sysfs node to allow configuring CZF_BYPASS, to enable platforms with low context-switching latency requirements. /sys/devices/17000000.gp10b/czf_bypass Values: 0 - always 1 - lateZ (default) 2 - single pass 3 - never The specified value will apply only to newly allocated contexts. Bug 1914014 Change-Id: Ibb9a8e86089acaadaa7260b00eedec5c80762d6f Signed-off-by: Peter Boonstoppel Reviewed-on: http://git-master/r/1478567 (cherry picked from commit 3bc022cb385b53f698b04f218db535e8162e8c94) Reviewed-on: http://git-master/r/1473820 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c | 36 ++++++++++++++++++++++++++++++++++- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 18 ++++++++++++++++++ 2 files changed, 53 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b') diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c index d42afb4c..ee14d00c 100644 --- a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c +++ b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c @@ -1,7 +1,7 @@ /* * GP10B specific sysfs files * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,6 +18,8 @@ #include "gk20a/gk20a.h" #include "gp10b_sysfs.h" +#include + #define ROOTRW (S_IRWXU|S_IRGRP|S_IROTH) static ssize_t ecc_enable_store(struct device *dev, @@ -49,12 +51,43 @@ static ssize_t ecc_enable_read(struct device *dev, static DEVICE_ATTR(ecc_enable, ROOTRW, ecc_enable_read, ecc_enable_store); + +static ssize_t czf_bypass_store(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct gk20a *g = get_gk20a(dev); + unsigned long val; + + if (kstrtoul(buf, 10, &val) < 0) + return -EINVAL; + + if (val >= 4) + return -EINVAL; + + g->gr.czf_bypass = val; + + return count; +} + +static ssize_t czf_bypass_read(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct gk20a *g = get_gk20a(dev); + + return sprintf(buf, "%d\n", g->gr.czf_bypass); +} + +static DEVICE_ATTR(czf_bypass, ROOTRW, czf_bypass_read, czf_bypass_store); + void gp10b_create_sysfs(struct device *dev) { struct gk20a *g = get_gk20a(dev); int error = 0; + g->gr.czf_bypass = gr_gpc0_prop_debug1_czf_bypass_init_v(); + error |= device_create_file(dev, &dev_attr_ecc_enable); + error |= device_create_file(dev, &dev_attr_czf_bypass); if (error) nvgpu_err(g, "Failed to create sysfs attributes!\n"); } @@ -62,4 +95,5 @@ void gp10b_create_sysfs(struct device *dev) void gp10b_remove_sysfs(struct device *dev) { device_remove_file(dev, &dev_attr_ecc_enable); + device_remove_file(dev, &dev_attr_czf_bypass); } diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index a43252de..1853aaec 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -27,6 +27,7 @@ #include "gk20a/gk20a.h" #include "gk20a/gr_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" +#include "gk20a/regops_gk20a.h" #include "gm20b/gr_gm20b.h" #include "gp10b/gr_gp10b.h" @@ -2304,6 +2305,22 @@ static void gr_gp10b_write_preemption_ptr(struct gk20a *g, } +int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch) +{ + struct nvgpu_dbg_gpu_reg_op ops; + + ops.op = REGOP(WRITE_32); + ops.type = REGOP(TYPE_GR_CTX); + ops.status = REGOP(STATUS_SUCCESS); + ops.value_hi = 0; + ops.and_n_mask_lo = gr_gpc0_prop_debug1_czf_bypass_m(); + ops.and_n_mask_hi = 0; + ops.offset = gr_gpc0_prop_debug1_r(); + ops.value_lo = gr_gpc0_prop_debug1_czf_bypass_f( + g->gr.czf_bypass); + + return __gr_gk20a_exec_ctx_ops(ch, &ops, 1, 1, 0, false); +} void gp10b_init_gr(struct gpu_ops *gops) { @@ -2355,4 +2372,5 @@ void gp10b_init_gr(struct gpu_ops *gops) gops->gr.load_smid_config = gr_gp10b_load_smid_config; gops->gr.set_boosted_ctx = gr_gp10b_set_boosted_ctx; gops->gr.update_boosted_ctx = gr_gp10b_update_boosted_ctx; + gops->gr.set_czf_bypass = gr_gp10b_set_czf_bypass; } -- cgit v1.2.2