From 36f02cf49729b32aa241cb9f1f235749da681dd1 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Fri, 11 Aug 2017 13:35:24 -0700 Subject: gpu: nvgpu: Add struct gk20a ptr to FUSE APIs Add a pointer to struct gk20a to the FUSE APIs. This helps QNX builds avoid any static data definitions. Also this change plumbs struct gk20a in some of the Linux clk code and fixes a few minor style nits. Change-Id: I27dfb2c4e9a352f784d6cead150460d8e9e808d3 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1537611 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Sourab Gupta Reviewed-by: svc-mobile-coverity Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 10 +++++----- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 9 ++++----- 2 files changed, 9 insertions(+), 10 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index d2b86e51..05fbeb21 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1600,15 +1600,15 @@ static void gr_gp10b_init_cyclestats(struct gk20a *g) static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) { - nvgpu_tegra_fuse_write_bypass(0x1); - nvgpu_tegra_fuse_write_access_sw(0x0); + nvgpu_tegra_fuse_write_bypass(g, 0x1); + nvgpu_tegra_fuse_write_access_sw(g, 0x0); if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) - nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x2); + nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x2); else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) - nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x1); + nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x1); else - nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0); + nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x0); } static void gr_gp10b_get_access_map(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index e9a9b922..da8044cd 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -378,13 +378,12 @@ static void pmu_dump_security_fuses_gp10b(struct gk20a *g) { u32 val; - nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", + nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0: 0x%x", gk20a_readl(g, fuse_opt_sec_debug_en_r())); - nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", + nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0: 0x%x", gk20a_readl(g, fuse_opt_priv_sec_en_r())); - nvgpu_tegra_fuse_read_gcplex_config_fuse(&val); - nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", - val); + nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val); + nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val); } static bool gp10b_is_pmu_supported(struct gk20a *g) -- cgit v1.2.2