From 227c6f7b7a499dd58e0db6859736cfe586ef0897 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 10 Aug 2018 14:09:36 -0700 Subject: gpu: nvgpu: Move fuse HAL to common Move implementation of fuse HAL to common/fuse. Also implements new fuse query functions for FBIO, FBP, TPC floorsweeping and security fuses. JIRA NVGPU-957 Change-Id: I55e256a4f1b59d50a721d4942907f70dc57467c4 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1797177 --- drivers/gpu/nvgpu/gp10b/fuse_gp10b.c | 105 ----------------------------------- drivers/gpu/nvgpu/gp10b/fuse_gp10b.h | 34 ------------ drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 16 +++++- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 14 ----- drivers/gpu/nvgpu/gp10b/pmu_gp10b.h | 1 - 5 files changed, 13 insertions(+), 157 deletions(-) delete mode 100644 drivers/gpu/nvgpu/gp10b/fuse_gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/fuse_gp10b.h (limited to 'drivers/gpu/nvgpu/gp10b') diff --git a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c deleted file mode 100644 index a79d5e1c..00000000 --- a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * GP10B FUSE - * - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include -#include - -#include "gk20a/gk20a.h" - -#include "gm20b/fuse_gm20b.h" - -#include "fuse_gp10b.h" - -#include - -int gp10b_fuse_check_priv_security(struct gk20a *g) -{ - u32 gcplex_config; - - if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); - nvgpu_log(g, gpu_dbg_info, "priv sec is disabled in fmodel"); - return 0; - } - - if (nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &gcplex_config)) { - nvgpu_err(g, "err reading gcplex config fuse, check fuse clk"); - return -EINVAL; - } - - if (gk20a_readl(g, fuse_opt_priv_sec_en_r())) { - /* - * all falcons have to boot in LS mode and this needs - * wpr_enabled set to 1 and vpr_auto_fetch_disable - * set to 0. In this case gmmu tries to pull wpr - * and vpr settings from tegra mc - */ - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); - if ((gcplex_config & - GCPLEX_CONFIG_WPR_ENABLED_MASK) && - !(gcplex_config & - GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK)) { - if (gk20a_readl(g, fuse_opt_sec_debug_en_r())) - nvgpu_log(g, gpu_dbg_info, - "gcplex_config = 0x%08x, " - "secure mode: ACR debug", - gcplex_config); - else - nvgpu_log(g, gpu_dbg_info, - "gcplex_config = 0x%08x, " - "secure mode: ACR non debug", - gcplex_config); - - } else { - nvgpu_err(g, "gcplex_config = 0x%08x " - "invalid wpr_enabled/vpr_auto_fetch_disable " - "with priv_sec_en", gcplex_config); - /* do not try to boot GPU */ - return -EINVAL; - } - } else { - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); - nvgpu_log(g, gpu_dbg_info, - "gcplex_config = 0x%08x, non secure mode", - gcplex_config); - } - - return 0; -} - -bool gp10b_fuse_is_opt_ecc_enable(struct gk20a *g) -{ - return gk20a_readl(g, fuse_opt_ecc_en_r()) != 0U; -} - -bool gp10b_fuse_is_opt_feature_override_disable(struct gk20a *g) -{ - return gk20a_readl(g, - fuse_opt_feature_fuses_override_disable_r()) != 0U; -} diff --git a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h deleted file mode 100644 index d9037e22..00000000 --- a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * GP10B FUSE - * - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef _NVGPU_GP10B_FUSE -#define _NVGPU_GP10B_FUSE - -struct gk20a; - -int gp10b_fuse_check_priv_security(struct gk20a *g); -bool gp10b_fuse_is_opt_ecc_enable(struct gk20a *g); -bool gp10b_fuse_is_opt_feature_override_disable(struct gk20a *g); - -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 7df17ed7..efd66b5d 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -36,6 +36,8 @@ #include "common/therm/therm_gp10b.h" #include "common/ltc/ltc_gm20b.h" #include "common/ltc/ltc_gp10b.h" +#include "common/fuse/fuse_gm20b.h" +#include "common/fuse/fuse_gp10b.h" #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -70,7 +72,6 @@ #include "gp10b.h" #include "hal_gp10b.h" -#include "fuse_gp10b.h" #include #include @@ -80,7 +81,6 @@ #include #include -#include #include #include #include @@ -597,7 +597,7 @@ static const struct gpu_ops gp10b_ops = { .pmu_pg_init_param = gp10b_pg_gr_init, .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, - .dump_secure_fuses = pmu_dump_security_fuses_gp10b, + .dump_secure_fuses = pmu_dump_security_fuses_gm20b, .reset_engine = gk20a_pmu_engine_reset, .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, .get_irqdest = gk20a_pmu_get_irqdest, @@ -702,6 +702,16 @@ static const struct gpu_ops gp10b_ops = { .is_opt_ecc_enable = gp10b_fuse_is_opt_ecc_enable, .is_opt_feature_override_disable = gp10b_fuse_is_opt_feature_override_disable, + .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, + .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, + .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, + .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, + .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, + .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, + .fuse_opt_priv_sec_en = gm20b_fuse_opt_priv_sec_en, + .read_vin_cal_fuse_rev = NULL, + .read_vin_cal_slope_intercept_fuse = NULL, + .read_vin_cal_gain_offset_fuse = NULL, }, .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics, .get_litter_value = gp10b_get_litter_value, diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 6ecb7957..d6497173 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -36,7 +36,6 @@ #include "pmu_gp10b.h" #include -#include #define gp10b_dbg_pmu(g, fmt, arg...) \ nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg) @@ -375,19 +374,6 @@ bool gp10b_is_priv_load(u32 falcon_id) return enable_status; } -/*Dump Security related fuses*/ -void pmu_dump_security_fuses_gp10b(struct gk20a *g) -{ - u32 val; - - nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0: 0x%x", - gk20a_readl(g, fuse_opt_sec_debug_en_r())); - nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0: 0x%x", - gk20a_readl(g, fuse_opt_priv_sec_en_r())); - nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val); - nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val); -} - bool gp10b_is_pmu_supported(struct gk20a *g) { return true; diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h index 44e0ec98..87c3ba79 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h @@ -35,7 +35,6 @@ int gp10b_init_pmu_setup_hw1(struct gk20a *g); void gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, struct pmu_pg_stats_data *pg_stat_data); int gp10b_pmu_setup_elpg(struct gk20a *g); -void pmu_dump_security_fuses_gp10b(struct gk20a *g); int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask); int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr); -- cgit v1.2.2