From 1da69dd8b2c60a11e112844dd4e9636a913a99a0 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Wed, 7 Jun 2017 17:32:56 -0700 Subject: gpu: nvgpu: Remove mm.get_iova_addr Remove the mm.get_iova_addr() HAL and replace it with a new HAL called mm.gpu_phys_addr(). This new HAL provides the real phys address that should be passed to the GPU from a physical address obtained from a scatter list. It also provides a mechanism by which the HAL code can add extra bits to a GPU physical address based on the attributes passed in. This is necessary during GMMU page table programming. Also remove the flags argument from the various address functions. This flag was used for adding an IO coherence bit to the GPU physical address which is not supported. JIRA NVGPU-30 Change-Id: I69af5b1c6bd905c4077c26c098fac101c6b41a33 Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1530864 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 1ac778e0..729ccc39 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -48,8 +48,7 @@ static int gp10b_init_mm_setup_hw(struct gk20a *g) g->ops.fb.set_mmu_page_size(g); gk20a_writel(g, fb_niso_flush_sysmem_addr_r(), - (g->ops.mm.get_iova_addr(g, g->mm.sysmem_flush.priv.sgt->sgl, 0) - >> 8ULL)); + nvgpu_mem_get_addr(g, &g->mm.sysmem_flush) >> 8ULL); g->ops.bus.bar1_bind(g, inst_block); @@ -343,7 +342,7 @@ static const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, static void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, struct vm_gk20a *vm) { - u64 pdb_addr = nvgpu_mem_get_base_addr(g, vm->pdb.mem, 0); + u64 pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem); u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); u32 pdb_addr_hi = u64_hi32(pdb_addr); -- cgit v1.2.2