From 07f6739285140d7c5335ddcb8996450966bfc175 Mon Sep 17 00:00:00 2001 From: Scott Long Date: Wed, 8 Aug 2018 18:30:09 -0700 Subject: gpu: nvgpu: switch gk20a nonstall ops to #defines Fix MISRA rule 10.1 violations involving gk20a_nonstall_ops enums by replacing them with with corresponding #defines. Because these values can be used in expressions that require unsigned values (e.g. bitwise OR) we cannot use enums. The g->ce2.isr_nonstall() function was previously returning an int that was a combination of gk20a_nonstall_ops enum bits which led to the violations. JIRA NVGPU-650 Change-Id: I6210aacec8829b3c8d339c5fe3db2f3069c67406 Signed-off-by: Scott Long Reviewed-on: https://git-master.nvidia.com/r/1796242 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/ce_gp10b.c | 8 ++++---- drivers/gpu/nvgpu/gp10b/ce_gp10b.h | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b') diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c index 048a9ba0..76179b78 100644 --- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c @@ -61,9 +61,9 @@ void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) return; } -int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) +u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) { - int ops = 0; + u32 ops = 0; u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); nvgpu_log(g, gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id); @@ -71,8 +71,8 @@ int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) if (ce_intr & ce_intr_status_nonblockpipe_pending_f()) { gk20a_writel(g, ce_intr_status_r(inst_id), ce_intr_status_nonblockpipe_pending_f()); - ops |= (gk20a_nonstall_ops_wakeup_semaphore | - gk20a_nonstall_ops_post_events); + ops |= (GK20A_NONSTALL_OPS_WAKEUP_SEMAPHORE | + GK20A_NONSTALL_OPS_POST_EVENTS); } return ops; diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h index 7b747751..fbf5e6f8 100644 --- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h @@ -1,7 +1,7 @@ /* * Pascal GPU series Copy Engine. * - * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -28,6 +28,6 @@ #include "gk20a/tsg_gk20a.h" void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base); -int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base); +u32 gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base); #endif /*__CE2_GP10B_H__*/ -- cgit v1.2.2