From aa7ee8dac0cb29ee3244c7eef77eac8e7fc34dba Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 27 Mar 2018 11:52:27 -0700 Subject: gpu: nvgpu: enhance pbus error reporting -Dump timeout save0 and save1 even if they could be unreliable when fecs_tgt in set in save0 . This is good to have for debug purposes. -Add priv_ring hal for decode_error_code -Decode fecs error code for supported error types Bug 1998067 Change-Id: I60cb6902d099df4a7df45fa624e44d9e0d46360f Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1683014 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h') diff --git a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h index 5b004a58..dd418e5b 100644 --- a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.h @@ -1,7 +1,7 @@ /* * GP10B PRIV ringmaster * - * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -27,5 +27,7 @@ struct gk20a; void gp10b_priv_ring_isr(struct gk20a *g); +void gp10b_priv_ring_decode_error_code(struct gk20a *g, + u32 error_code); #endif /*__PRIV_RING_GP10B_H__*/ -- cgit v1.2.2