From aa7ee8dac0cb29ee3244c7eef77eac8e7fc34dba Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Tue, 27 Mar 2018 11:52:27 -0700 Subject: gpu: nvgpu: enhance pbus error reporting -Dump timeout save0 and save1 even if they could be unreliable when fecs_tgt in set in save0 . This is good to have for debug purposes. -Add priv_ring hal for decode_error_code -Decode fecs error code for supported error types Bug 1998067 Change-Id: I60cb6902d099df4a7df45fa624e44d9e0d46360f Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1683014 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c index 0fac76f2..12cd2a84 100644 --- a/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c @@ -64,7 +64,7 @@ static const char *const error_type_badf5xyy[] = { "pri route error" }; -static void gp10b_priv_ring_decode_error_code(struct gk20a *g, +void gp10b_priv_ring_decode_error_code(struct gk20a *g, u32 error_code) { u32 error_type, error_type_index; @@ -141,7 +141,8 @@ void gp10b_priv_ring_isr(struct gk20a *g) pri_ringstation_sys_priv_error_info_subid_v(error_info), pri_ringstation_sys_priv_error_info_priv_level_v(error_info), error_code); - gp10b_priv_ring_decode_error_code(g, error_code); + if (g->ops.priv_ring.decode_error_code) + g->ops.priv_ring.decode_error_code(g, error_code); } if (status1) { @@ -166,7 +167,9 @@ void gp10b_priv_ring_isr(struct gk20a *g) pri_ringstation_gpc_gpc0_priv_error_info_priv_level_v(error_info), error_code); - gp10b_priv_ring_decode_error_code(g, error_code); + if (g->ops.priv_ring.decode_error_code) + g->ops.priv_ring.decode_error_code(g, + error_code); status1 = status1 & (~(BIT(gpc))); if (!status1) -- cgit v1.2.2