From f9e55fbaf66c024125a19e1a773a1a4f0e9648f4 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Mon, 7 May 2018 11:42:33 +0530 Subject: gpu: nvgpu: Add LDIV slowdown factor in INIT cmd. PMU ucode is updated to include LDIV slowdown factor in gr_init_param command. - Defined a new version gr_init_param_v2. - Updated the PMU FW version code. - Set the LDIV slowdown factor to 0x1e by default. - Added sysfs entry to program ldiv_slowdown factor at runtime. Bug 200391931 Change-Id: Ic66049588c3b20e934faff3f29283f66c30303e4 Signed-off-by: Deepak Goyal Reviewed-on: https://git-master.nvidia.com/r/1674208 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 49ad3920..c94d580a 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B PMU * - * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -233,13 +233,15 @@ int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) memset(&cmd, 0, sizeof(struct pmu_cmd)); cmd.hdr.unit_id = PMU_UNIT_PG; cmd.hdr.size = PMU_CMD_HDR_SIZE + - sizeof(struct pmu_pg_cmd_gr_init_param); - cmd.cmd.pg.gr_init_param.cmd_type = + sizeof(struct pmu_pg_cmd_gr_init_param_v2); + cmd.cmd.pg.gr_init_param_v2.cmd_type = PMU_PG_CMD_ID_PG_PARAM; - cmd.cmd.pg.gr_init_param.sub_cmd_id = + cmd.cmd.pg.gr_init_param_v2.sub_cmd_id = PMU_PG_PARAM_CMD_GR_INIT_PARAM; - cmd.cmd.pg.gr_init_param.featuremask = + cmd.cmd.pg.gr_init_param_v2.featuremask = NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING; + cmd.cmd.pg.gr_init_param_v2.ldiv_slowdown_factor = + g->ldiv_slowdown_factor; gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM "); nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, -- cgit v1.2.2