From 5452d161544f40778f75dda06bfddb14bcb48707 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 11 Dec 2014 12:40:03 +0530 Subject: gpu: nvgpu: gp10b: gpmu elpg support Temporally used gm20b elpg sequencing values for gp10b elpg. Bug 1525971 Change-Id: Ibffb5180979be9d7ee68cad67cd6f10cf23590c3 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/662517 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 167 ++++++++++++++++++++++++++++++++++++ 1 file changed, 167 insertions(+) create mode 100644 drivers/gpu/nvgpu/gp10b/pmu_gp10b.c (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c new file mode 100644 index 00000000..3db0d4c3 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -0,0 +1,167 @@ +/* + * GP10B PMU + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. +* + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include /* for udelay */ +#include "gk20a/gk20a.h" +#include "gk20a/pmu_gk20a.h" +#include "gm20b/acr_gm20b.h" +#include "gm20b/pmu_gm20b.h" + +#include "pmu_gp10b.h" + +/*! + * Structure/object which single register write need to be done during PG init + * sequence to set PROD values. + */ +struct pg_init_sequence_list { + u32 regaddr; + u32 writeval; +}; + +/* PROD settings for ELPG sequencing registers*/ +static struct pg_init_sequence_list _pginitseq_gm20b[] = { + { 0x0010ab10, 0x8180}, + { 0x0010e118, 0x83828180}, + { 0x0010e068, 0}, + { 0x0010e06c, 0x00000080}, + { 0x0010e06c, 0x00000081}, + { 0x0010e06c, 0x00000082}, + { 0x0010e06c, 0x00000083}, + { 0x0010e06c, 0x00000084}, + { 0x0010e06c, 0x00000085}, + { 0x0010e06c, 0x00000086}, + { 0x0010e06c, 0x00000087}, + { 0x0010e06c, 0x00000088}, + { 0x0010e06c, 0x00000089}, + { 0x0010e06c, 0x0000008a}, + { 0x0010e06c, 0x0000008b}, + { 0x0010e06c, 0x0000008c}, + { 0x0010e06c, 0x0000008d}, + { 0x0010e06c, 0x0000008e}, + { 0x0010e06c, 0x0000008f}, + { 0x0010e06c, 0x00000090}, + { 0x0010e06c, 0x00000091}, + { 0x0010e06c, 0x00000092}, + { 0x0010e06c, 0x00000093}, + { 0x0010e06c, 0x00000094}, + { 0x0010e06c, 0x00000095}, + { 0x0010e06c, 0x00000096}, + { 0x0010e06c, 0x00000097}, + { 0x0010e06c, 0x00000098}, + { 0x0010e06c, 0x00000099}, + { 0x0010e06c, 0x0000009a}, + { 0x0010e06c, 0x0000009b}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010ab14, 0x00000000}, + { 0x0010ab18, 0x00000000}, + { 0x0010e024, 0x00000000}, + { 0x0010e028, 0x00000000}, + { 0x0010e11c, 0x00000000}, + { 0x0010e120, 0x00000000}, + { 0x0010ab1c, 0x02010155}, + { 0x0010e020, 0x001b1b55}, + { 0x0010e124, 0x01030355}, + { 0x0010ab20, 0x89abcdef}, + { 0x0010ab24, 0x00000000}, + { 0x0010e02c, 0x89abcdef}, + { 0x0010e030, 0x00000000}, + { 0x0010e128, 0x89abcdef}, + { 0x0010e12c, 0x00000000}, + { 0x0010ab28, 0x74444444}, + { 0x0010ab2c, 0x70000000}, + { 0x0010e034, 0x74444444}, + { 0x0010e038, 0x70000000}, + { 0x0010e130, 0x74444444}, + { 0x0010e134, 0x70000000}, + { 0x0010ab30, 0x00000000}, + { 0x0010ab34, 0x00000001}, + { 0x00020004, 0x00000000}, + { 0x0010e138, 0x00000000}, + { 0x0010e040, 0x00000000}, +}; + +static int gp10b_pmu_setup_elpg(struct gk20a *g) +{ + int ret = 0; + u32 reg_writes; + u32 index; + + gk20a_dbg_fn(""); + + if (g->elpg_enabled) { + reg_writes = ((sizeof(_pginitseq_gm20b) / + sizeof((_pginitseq_gm20b)[0]))); + /* Initialize registers with production values*/ + for (index = 0; index < reg_writes; index++) { + gk20a_writel(g, _pginitseq_gm20b[index].regaddr, + _pginitseq_gm20b[index].writeval); + } + } + + gk20a_dbg_fn("done"); + return ret; +} + +void gp10b_init_pmu_ops(struct gpu_ops *gops) +{ + if (gops->privsecurity) { + gm20b_init_secure_pmu(gops); + gops->pmu.init_wpr_region = NULL; + } else { + gk20a_init_pmu_ops(gops); + gops->pmu.init_wpr_region = NULL; + } + gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg; + gops->pmu.lspmuwprinitdone = false; + gops->pmu.fecsbootstrapdone = false; + gops->pmu.fecsrecoveryinprogress = 0; +} -- cgit v1.2.2 From c5425c5a1b3795e9a7d0887eccd025509186bcd1 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 16 Apr 2015 16:16:47 +0530 Subject: gpu: nvgpu: gp10b:inherit gm20b acr init wpr func -method gm20b_pmu_init_acr() used for gp10b acr init wpr region Bug 200085428 Change-Id: I897aa42b0a8ef7478d4b3f64fe1834532d35b303 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/732213 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu Tested-by: Vijayakumar Subbu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 3db0d4c3..4ba0f997 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B PMU * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -155,7 +155,7 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) { if (gops->privsecurity) { gm20b_init_secure_pmu(gops); - gops->pmu.init_wpr_region = NULL; + gops->pmu.init_wpr_region = gm20b_pmu_init_acr; } else { gk20a_init_pmu_ops(gops); gops->pmu.init_wpr_region = NULL; -- cgit v1.2.2 From faa1e5d82b8c3a2d125f04788f8146ba9b9b186c Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Fri, 17 Apr 2015 11:43:40 +0530 Subject: gpu: nvgpu: gp10b: update elpg sequencing value - Added final elpg sequencing value - by default elpg is disabled. Bug 1525971 Change-Id: I2c306d9f03e361560a95fcfa723eafe14d004191 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/732574 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 201 ++++++++++++++++++------------------ 1 file changed, 101 insertions(+), 100 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 4ba0f997..9ecf3964 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -31,102 +31,103 @@ struct pg_init_sequence_list { }; /* PROD settings for ELPG sequencing registers*/ -static struct pg_init_sequence_list _pginitseq_gm20b[] = { - { 0x0010ab10, 0x8180}, - { 0x0010e118, 0x83828180}, - { 0x0010e068, 0}, - { 0x0010e06c, 0x00000080}, - { 0x0010e06c, 0x00000081}, - { 0x0010e06c, 0x00000082}, - { 0x0010e06c, 0x00000083}, - { 0x0010e06c, 0x00000084}, - { 0x0010e06c, 0x00000085}, - { 0x0010e06c, 0x00000086}, - { 0x0010e06c, 0x00000087}, - { 0x0010e06c, 0x00000088}, - { 0x0010e06c, 0x00000089}, - { 0x0010e06c, 0x0000008a}, - { 0x0010e06c, 0x0000008b}, - { 0x0010e06c, 0x0000008c}, - { 0x0010e06c, 0x0000008d}, - { 0x0010e06c, 0x0000008e}, - { 0x0010e06c, 0x0000008f}, - { 0x0010e06c, 0x00000090}, - { 0x0010e06c, 0x00000091}, - { 0x0010e06c, 0x00000092}, - { 0x0010e06c, 0x00000093}, - { 0x0010e06c, 0x00000094}, - { 0x0010e06c, 0x00000095}, - { 0x0010e06c, 0x00000096}, - { 0x0010e06c, 0x00000097}, - { 0x0010e06c, 0x00000098}, - { 0x0010e06c, 0x00000099}, - { 0x0010e06c, 0x0000009a}, - { 0x0010e06c, 0x0000009b}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010ab14, 0x00000000}, - { 0x0010ab18, 0x00000000}, - { 0x0010e024, 0x00000000}, - { 0x0010e028, 0x00000000}, - { 0x0010e11c, 0x00000000}, - { 0x0010e120, 0x00000000}, - { 0x0010ab1c, 0x02010155}, - { 0x0010e020, 0x001b1b55}, - { 0x0010e124, 0x01030355}, - { 0x0010ab20, 0x89abcdef}, - { 0x0010ab24, 0x00000000}, - { 0x0010e02c, 0x89abcdef}, - { 0x0010e030, 0x00000000}, - { 0x0010e128, 0x89abcdef}, - { 0x0010e12c, 0x00000000}, - { 0x0010ab28, 0x74444444}, - { 0x0010ab2c, 0x70000000}, - { 0x0010e034, 0x74444444}, - { 0x0010e038, 0x70000000}, - { 0x0010e130, 0x74444444}, - { 0x0010e134, 0x70000000}, - { 0x0010ab30, 0x00000000}, - { 0x0010ab34, 0x00000001}, - { 0x00020004, 0x00000000}, - { 0x0010e138, 0x00000000}, - { 0x0010e040, 0x00000000}, +static struct pg_init_sequence_list _pginitseq_gp10b[] = { + {0x0010ab10, 0x0000868B} , + {0x0010e118, 0x8590848F} , + {0x0010e000, 0} , + {0x0010e06c, 0x000000A3} , + {0x0010e06c, 0x000000A0} , + {0x0010e06c, 0x00000095} , + {0x0010e06c, 0x000000A6} , + {0x0010e06c, 0x0000008C} , + {0x0010e06c, 0x00000080} , + {0x0010e06c, 0x00000081} , + {0x0010e06c, 0x00000087} , + {0x0010e06c, 0x00000088} , + {0x0010e06c, 0x0000008D} , + {0x0010e06c, 0x000000A00} , + {0x0010e06c, 0x000000A01} , + {0x0010e06c, 0x000000A02} , + {0x0010e06c, 0x000000A03} , + {0x0010e06c, 0x000000A04} , + {0x0010e06c, 0x000000A05} , + {0x0010e06c, 0x000000A06} , + {0x0010e06c, 0x000000A07} , + {0x0010e06c, 0x000000A08} , + {0x0010e06c, 0x000000A09} , + {0x0010e06c, 0x000000950} , + {0x0010e06c, 0x000000951} , + {0x0010e06c, 0x000000952} , + {0x0010e06c, 0x000000953} , + {0x0010e06c, 0x000000954} , + {0x0010e06c, 0x000000955} , + {0x0010e06c, 0x000000956} , + {0x0010e06c, 0x000000957} , + {0x0010ab14, 0x00000000} , + {0x0010e024, 0x00000000} , + {0x0010e028, 0x00000000} , + {0x0010e11c, 0x00000000} , + {0x0010ab1c, 0x140B0B55} , + {0x0010e020, 0x0E262655} , + {0x0010e124, 0x25101055} , + {0x0010ab20, 0x89abcdef} , + {0x0010ab24, 0x00000000} , + {0x0010e02c, 0x89abcdef} , + {0x0010e030, 0x00000000} , + {0x0010e128, 0x89abcdef} , + {0x0010e12c, 0x00000000} , + {0x0010ab28, 0x75555555} , + {0x0010ab2c, 0x70000000} , + {0x0010e034, 0x75555555} , + {0x0010e038, 0x70000000} , + {0x0010e130, 0x75555555} , + {0x0010e134, 0x70000000} , + {0x0010ab30, 0x00000000} , + {0x0010ab34, 0x00000001} , + {0x00020004, 0x00000000} , + {0x0010e138, 0x00000000} , + {0x0010e040, 0x00000000} , + {0x0010e168, 0x00000000} , + {0x0010e114, 0x0000A5A4} , + {0x0010e110, 0x00000000} , + {0x0010e10c, 0x8590848F} , + {0x0010e05c, 0x00000000} , + {0x0010e044, 0x00000000} , + {0x0010a644, 0x0000868B} , + {0x0010a648, 0x00000000 } , + {0x0010a64c, 0x00829493 } , + {0x0010a650, 0x00000000} , + {0x0010e000, 0} , + {0x0010e068, 0x000000A3} , + {0x0010e068, 0x000000A0} , + {0x0010e068, 0x00000095} , + {0x0010e068, 0x000000A6} , + {0x0010e068, 0x0000008C} , + {0x0010e068, 0x00000080} , + {0x0010e068, 0x00000081} , + {0x0010e068, 0x00000087} , + {0x0010e068, 0x00000088} , + {0x0010e068, 0x0000008D} , + {0x0010e068, 0x000000A00} , + {0x0010e068, 0x000000A01} , + {0x0010e068, 0x000000A02} , + {0x0010e068, 0x000000A03} , + {0x0010e068, 0x000000A04} , + {0x0010e068, 0x000000A05} , + {0x0010e068, 0x000000A06} , + {0x0010e068, 0x000000A07} , + {0x0010e068, 0x000000A08} , + {0x0010e068, 0x000000A09} , + {0x0010e068, 0x000000950} , + {0x0010e068, 0x000000951} , + {0x0010e068, 0x000000952} , + {0x0010e068, 0x000000953} , + {0x0010e068, 0x000000954} , + {0x0010e068, 0x000000955} , + {0x0010e068, 0x000000956} , + {0x0010e068, 0x000000957} , + {0x0010e000, 0} , + {0x0010e004, 0x0000008E}, }; static int gp10b_pmu_setup_elpg(struct gk20a *g) @@ -138,12 +139,12 @@ static int gp10b_pmu_setup_elpg(struct gk20a *g) gk20a_dbg_fn(""); if (g->elpg_enabled) { - reg_writes = ((sizeof(_pginitseq_gm20b) / - sizeof((_pginitseq_gm20b)[0]))); + reg_writes = ((sizeof(_pginitseq_gp10b) / + sizeof((_pginitseq_gp10b)[0]))); /* Initialize registers with production values*/ for (index = 0; index < reg_writes; index++) { - gk20a_writel(g, _pginitseq_gm20b[index].regaddr, - _pginitseq_gm20b[index].writeval); + gk20a_writel(g, _pginitseq_gp10b[index].regaddr, + _pginitseq_gp10b[index].writeval); } } -- cgit v1.2.2 From 588d8975bda1f740d54af516b7a04521810c3735 Mon Sep 17 00:00:00 2001 From: Vijayakumar Date: Fri, 17 Apr 2015 09:49:50 +0530 Subject: gpu:nvgpu:gp10b: support secure gpccs changes bug 200080684 Change-Id: I5888939017877a50b9bd596393ee8ad1547c18e5 Signed-off-by: Vijayakumar Reviewed-on: http://git-master/r/732535 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 9ecf3964..b8b985b3 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -164,5 +164,4 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg; gops->pmu.lspmuwprinitdone = false; gops->pmu.fecsbootstrapdone = false; - gops->pmu.fecsrecoveryinprogress = 0; } -- cgit v1.2.2 From 4c074ba3021e7fd52b10a5e7267b36e07da5660a Mon Sep 17 00:00:00 2001 From: Vijayakumar Date: Mon, 25 May 2015 15:01:04 +0530 Subject: gpu: nvgpu: gp10b: dma support for secure gpccs bug 200080684 Change-Id: I013a0ca7762f6cca0498bd282303597bf683cb7d Signed-off-by: Vijayakumar Reviewed-on: http://git-master/r/746737 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 74 +++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index b8b985b3..7b806026 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -21,6 +21,8 @@ #include "pmu_gp10b.h" +#define gp10b_dbg_pmu(fmt, arg...) \ + gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) /*! * Structure/object which single register write need to be done during PG init * sequence to set PROD values. @@ -130,6 +132,76 @@ static struct pg_init_sequence_list _pginitseq_gp10b[] = { {0x0010e004, 0x0000008E}, }; +void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, + u32 flags) +{ + struct pmu_gk20a *pmu = &g->pmu; + struct pmu_cmd cmd; + u32 seq; + + gk20a_dbg_fn(""); + + gp10b_dbg_pmu("wprinit status = %x\n", g->ops.pmu.lspmuwprinitdone); + if (g->ops.pmu.lspmuwprinitdone) { + /* send message to load FECS falcon */ + memset(&cmd, 0, sizeof(struct pmu_cmd)); + cmd.hdr.unit_id = PMU_UNIT_ACR; + cmd.hdr.size = PMU_CMD_HDR_SIZE + + sizeof(struct pmu_acr_cmd_bootstrap_multiple_falcons); + cmd.cmd.acr.boot_falcons.cmd_type = + PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS; + cmd.cmd.acr.boot_falcons.flags = flags; + cmd.cmd.acr.boot_falcons.falconidmask = + falconidmask; + cmd.cmd.acr.boot_falcons.usevamask = + 1 << LSF_FALCON_ID_GPCCS; + cmd.cmd.acr.boot_falcons.wprvirtualbase.lo = + u64_lo32(g->pmu.wpr_buf.gpu_va); + cmd.cmd.acr.boot_falcons.wprvirtualbase.hi = + u64_hi32(g->pmu.wpr_buf.gpu_va); + gp10b_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n", + falconidmask); + gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, + pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0); + } + + gk20a_dbg_fn("done"); + return; +} + +int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) +{ + u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; + + /* GM20B PMU supports loading FECS and GPCCS only */ + if (falconidmask == 0) + return -EINVAL; + if (falconidmask & ~((1 << LSF_FALCON_ID_FECS) | + (1 << LSF_FALCON_ID_GPCCS))) + return -EINVAL; + g->ops.pmu.lsfloadedfalconid = 0; + /* check whether pmu is ready to bootstrap lsf if not wait for it */ + if (!g->ops.pmu.lspmuwprinitdone) { + pmu_wait_message_cond(&g->pmu, + gk20a_get_gr_idle_timeout(g), + &g->ops.pmu.lspmuwprinitdone, 1); + /* check again if it still not ready indicate an error */ + if (!g->ops.pmu.lspmuwprinitdone) { + gk20a_err(dev_from_gk20a(g), + "PMU not ready to load LSF"); + return -ETIMEDOUT; + } + } + /* load falcon(s) */ + gp10b_pmu_load_multiple_falcons(g, falconidmask, flags); + pmu_wait_message_cond(&g->pmu, + gk20a_get_gr_idle_timeout(g), + &g->ops.pmu.lsfloadedfalconid, falconidmask); + if (g->ops.pmu.lsfloadedfalconid != falconidmask) + return -ETIMEDOUT; + return 0; +} + static int gp10b_pmu_setup_elpg(struct gk20a *g) { int ret = 0; @@ -157,8 +229,10 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) if (gops->privsecurity) { gm20b_init_secure_pmu(gops); gops->pmu.init_wpr_region = gm20b_pmu_init_acr; + gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; } else { gk20a_init_pmu_ops(gops); + gops->pmu.load_lsfalcon_ucode = NULL; gops->pmu.init_wpr_region = NULL; } gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg; -- cgit v1.2.2 From c965e6655800afffd3d4e3d73f28198adef7a118 Mon Sep 17 00:00:00 2001 From: Vijayakumar Date: Wed, 1 Jul 2015 12:50:26 +0530 Subject: gpu: nvgpu: gp10b: make local function 'static' Fixed the following sparse warning by making the local function as static: - symbol 'gp10b_pmu_load_multiple_falcons' was not declared. Should it be static? - symbol 'gp10b_load_falcon_ucode' was not declared. Should it be static? bug 200067946 Change-Id: I67d865aef6f57bf614db351929cd4bb1b6077c00 Signed-off-by: Vijayakumar Reviewed-on: http://git-master/r/764646 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Amit Sharma (SW-TEGRA) GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 7b806026..2a8d968c 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -132,7 +132,7 @@ static struct pg_init_sequence_list _pginitseq_gp10b[] = { {0x0010e004, 0x0000008E}, }; -void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, +static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, u32 flags) { struct pmu_gk20a *pmu = &g->pmu; @@ -169,7 +169,7 @@ void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, return; } -int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) +static int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) { u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; -- cgit v1.2.2 From 892ed4317b581abc85a481c48272f35b36410b65 Mon Sep 17 00:00:00 2001 From: Supriya Date: Thu, 6 Aug 2015 16:39:39 +0530 Subject: gpu: nvgpu: gp10b: Fix NS boot transcfg Bug 1667322 Accomodate for transcfg address change Change-Id: I83c5d4921040258a480df44a69792c721ff88f05 Signed-off-by: Supriya Reviewed-on: http://git-master/r/779764 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 2a8d968c..dcf28edf 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -232,6 +232,8 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; } else { gk20a_init_pmu_ops(gops); + gops->pmu.pmu_setup_hw_and_bootstrap = + gm20b_init_nspmu_setup_hw1; gops->pmu.load_lsfalcon_ucode = NULL; gops->pmu.init_wpr_region = NULL; } -- cgit v1.2.2 From 83955e553c9111e544eaa9d269347a61cfe3fa71 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Sun, 13 Sep 2015 13:44:01 -0700 Subject: gpu: nvgpu: priv load for gpccs load. - clear mask to load gpcss with priv load. Bug n/a Change-Id: I21522bda83c4dd5c665d47ae334b9fed5cb8ec74 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/798406 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index dcf28edf..f29bcbad 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -153,8 +153,7 @@ static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, cmd.cmd.acr.boot_falcons.flags = flags; cmd.cmd.acr.boot_falcons.falconidmask = falconidmask; - cmd.cmd.acr.boot_falcons.usevamask = - 1 << LSF_FALCON_ID_GPCCS; + cmd.cmd.acr.boot_falcons.usevamask = 0; cmd.cmd.acr.boot_falcons.wprvirtualbase.lo = u64_lo32(g->pmu.wpr_buf.gpu_va); cmd.cmd.acr.boot_falcons.wprvirtualbase.hi = -- cgit v1.2.2 From cc1b124d5a6fdabdd541d3ddd0570a264b46be0c Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Mon, 14 Sep 2015 10:03:05 -0700 Subject: gpu: nvgpu: HAL to write DMATRFBASE - Must write DMATRFBASE1 to 0 whenever DMATRFBASE is written. Bug 200137618 Change-Id: Id8526d1bafbd116ffc4d8018983791fe9e9fa604 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/798780 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index f29bcbad..529491d0 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -20,6 +20,7 @@ #include "gm20b/pmu_gm20b.h" #include "pmu_gp10b.h" +#include "hw_pwr_gp10b.h" #define gp10b_dbg_pmu(fmt, arg...) \ gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) @@ -223,6 +224,14 @@ static int gp10b_pmu_setup_elpg(struct gk20a *g) return ret; } +void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr) +{ + gk20a_writel(g, pwr_falcon_dmatrfbase_r(), + addr); + gk20a_writel(g, pwr_falcon_dmatrfbase1_r(), + 0x0); +} + void gp10b_init_pmu_ops(struct gpu_ops *gops) { if (gops->privsecurity) { @@ -239,4 +248,5 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg; gops->pmu.lspmuwprinitdone = false; gops->pmu.fecsbootstrapdone = false; + gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase; } -- cgit v1.2.2 From 17bc6e64577f2b0ce2c26b5ed4a8b7a8d06eede2 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 18 Sep 2015 14:15:32 +0530 Subject: gpu: nvgpu: fix sparse warning Fix below sparse warning by declaring gp10b_write_dmatrfbase() as static kernel-t18x/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c:227:6: warning: symbol 'gp10b_write_dmatrfbase' was not declared. Should it be static? Bug 200088648 Change-Id: I3bd2eeaeb7234ab54d7e9342a7512ec28388f751 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/801213 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 529491d0..a4d7a0f7 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -224,7 +224,7 @@ static int gp10b_pmu_setup_elpg(struct gk20a *g) return ret; } -void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr) +static void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr) { gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr); -- cgit v1.2.2 From 1ef64423f91a4add0351bed5bf55577768ccebf2 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Mon, 21 Sep 2015 14:57:54 -0700 Subject: gpu: nvgpu: ELPG init & statistics update - Required init param to start elpg - change in statistics dump Bug 1684939 Change-Id: Icc482c08303d0870ec2e1c18a845074968b15e77 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/802455 Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom Reviewed-on: http://git-master/r/806194 Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 56 +++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index a4d7a0f7..6832bf41 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -202,6 +202,60 @@ static int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) return 0; } +static void pmu_handle_gr_param_msg(struct gk20a *g, struct pmu_msg *msg, + void *param, u32 handle, u32 status) +{ + gk20a_dbg_fn(""); + + if (status != 0) { + gk20a_err(dev_from_gk20a(g), "GR PARAM cmd aborted"); + /* TBD: disable ELPG */ + return; + } + + gp10b_dbg_pmu("GR PARAM is acknowledged from PMU %x \n", + msg->msg.pg.msg_type); + + return; +} + +static int gp10b_pg_gr_init(struct gk20a *g, u8 grfeaturemask) +{ + struct pmu_gk20a *pmu = &g->pmu; + struct pmu_cmd cmd; + u32 seq; + + memset(&cmd, 0, sizeof(struct pmu_cmd)); + cmd.hdr.unit_id = PMU_UNIT_PG; + cmd.hdr.size = PMU_CMD_HDR_SIZE + + sizeof(struct pmu_pg_cmd_gr_init_param); + cmd.cmd.pg.gr_init_param.cmd_type = + PMU_PG_CMD_ID_PG_PARAM; + cmd.cmd.pg.gr_init_param.sub_cmd_id = + PMU_PG_PARAM_CMD_GR_INIT_PARAM; + cmd.cmd.pg.gr_init_param.featuremask = + grfeaturemask; + + gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM %x", grfeaturemask); + gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, + pmu_handle_gr_param_msg, pmu, &seq, ~0); + + return 0; +} +void gp10b_pmu_elpg_statistics(struct gk20a *g, + u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt) +{ + struct pmu_gk20a *pmu = &g->pmu; + struct pmu_pg_stats_v1 stats; + + pmu_copy_from_dmem(pmu, pmu->stat_dmem_offset, + (u8 *)&stats, sizeof(struct pmu_pg_stats_v1), 0); + + *ingating_time = stats.total_sleep_timeus; + *ungating_time = stats.total_nonsleep_timeus; + *gating_cnt = stats.entry_count; +} + static int gp10b_pmu_setup_elpg(struct gk20a *g) { int ret = 0; @@ -249,4 +303,6 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.lspmuwprinitdone = false; gops->pmu.fecsbootstrapdone = false; gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase; + gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics; + gops->pmu.pmu_pg_grinit_param = gp10b_pg_gr_init; } -- cgit v1.2.2 From c9da53da4e595271fc6a9639cf1907d84061e356 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 2 Oct 2015 17:27:32 +0530 Subject: gpu: nvgpu: fix sparse warning fix below sparse warning drivers/gpu/nvgpu/gm20b/gr_gm20b.c:1055:6: warning: symbol 'gr_gm20b_enable_cde_in_fecs' was not declared. Should it be static? Bug 200088648 Change-Id: I862100d76f2ed5669d15a8f3b8cb9211df7f98ee Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/810394 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Amit Sharma (SW-TEGRA) GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 6832bf41..77727ff2 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -242,7 +242,7 @@ static int gp10b_pg_gr_init(struct gk20a *g, u8 grfeaturemask) return 0; } -void gp10b_pmu_elpg_statistics(struct gk20a *g, +static void gp10b_pmu_elpg_statistics(struct gk20a *g, u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt) { struct pmu_gk20a *pmu = &g->pmu; -- cgit v1.2.2 From 8066fc9b7be169e29f294a34eaa6e699f13baa5d Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Tue, 6 Oct 2015 09:37:11 -0700 Subject: gpu:nvgpu: gp10b: modify gpmu hw init Modify gpmu hwinit to take gp10b specific register offsets in non-secure GPMU boot path. Bug 1685722 Change-Id: Id6696fb20c4fd40ee1b168c952a438771721c792 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/812271 (cherry picked from commit b9408892dd08beca5f4b2e056287a2bc28ccff0e) Reviewed-on: http://git-master/r/813979 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 39 +++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 77727ff2..df515d1b 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -286,6 +286,44 @@ static void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr) 0x0); } +static int gp10b_init_pmu_setup_hw1(struct gk20a *g) +{ + struct pmu_gk20a *pmu = &g->pmu; + int err; + + gk20a_dbg_fn(""); + + mutex_lock(&pmu->isr_mutex); + pmu_reset(pmu); + pmu->isr_enabled = true; + mutex_unlock(&pmu->isr_mutex); + + /* setup apertures - virtual */ + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), + pwr_fbif_transcfg_mem_type_virtual_f()); + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), + pwr_fbif_transcfg_mem_type_virtual_f()); + + /* setup apertures - physical */ + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), + pwr_fbif_transcfg_mem_type_physical_f() | + pwr_fbif_transcfg_target_local_fb_f()); + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), + pwr_fbif_transcfg_mem_type_physical_f() | + pwr_fbif_transcfg_target_coherent_sysmem_f()); + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), + pwr_fbif_transcfg_mem_type_physical_f() | + pwr_fbif_transcfg_target_noncoherent_sysmem_f()); + + err = pmu_bootstrap(pmu); + if (err) + return err; + + gk20a_dbg_fn("done"); + return 0; + +} + void gp10b_init_pmu_ops(struct gpu_ops *gops) { if (gops->privsecurity) { @@ -299,6 +337,7 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.load_lsfalcon_ucode = NULL; gops->pmu.init_wpr_region = NULL; } + gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg; gops->pmu.lspmuwprinitdone = false; gops->pmu.fecsbootstrapdone = false; -- cgit v1.2.2 From 50f5c87f1cb452fc4338cf932c35428aeee57dd7 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Mon, 12 Oct 2015 13:54:43 +0530 Subject: gpu: nvgpu: gp10b non-secure gpmu hw init call gp10b_init_pmu_setup_hw1 during non-secure boot only. Change-Id: Ia90474c7c04edd9be029d013f1da5f73de1b5326 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/815843 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index df515d1b..57accfb0 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -336,8 +336,8 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gm20b_init_nspmu_setup_hw1; gops->pmu.load_lsfalcon_ucode = NULL; gops->pmu.init_wpr_region = NULL; + gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; } - gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg; gops->pmu.lspmuwprinitdone = false; gops->pmu.fecsbootstrapdone = false; -- cgit v1.2.2 From b76acb0ef67d45fe775e915fed2648da03cfc424 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Tue, 24 Nov 2015 10:15:28 +0530 Subject: gpu: nvgpu: ELPG prod values update Bug 200151348 Change-Id: I44851b69adfe9c6bf5d4c897730d6da7df9bedd8 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/836877 (cherry picked from commit 69de3f3c439f544fd5f9223f5663010f5ec80193) Reviewed-on: http://git-master/r/837228 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 88 ++++++++++++++++++------------------- 1 file changed, 44 insertions(+), 44 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 57accfb0..dc7539a8 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -48,42 +48,42 @@ static struct pg_init_sequence_list _pginitseq_gp10b[] = { {0x0010e06c, 0x00000087} , {0x0010e06c, 0x00000088} , {0x0010e06c, 0x0000008D} , - {0x0010e06c, 0x000000A00} , - {0x0010e06c, 0x000000A01} , - {0x0010e06c, 0x000000A02} , - {0x0010e06c, 0x000000A03} , - {0x0010e06c, 0x000000A04} , - {0x0010e06c, 0x000000A05} , - {0x0010e06c, 0x000000A06} , - {0x0010e06c, 0x000000A07} , - {0x0010e06c, 0x000000A08} , - {0x0010e06c, 0x000000A09} , - {0x0010e06c, 0x000000950} , - {0x0010e06c, 0x000000951} , - {0x0010e06c, 0x000000952} , - {0x0010e06c, 0x000000953} , - {0x0010e06c, 0x000000954} , - {0x0010e06c, 0x000000955} , - {0x0010e06c, 0x000000956} , - {0x0010e06c, 0x000000957} , + {0x0010e06c, 0x00000082} , + {0x0010e06c, 0x00000083} , + {0x0010e06c, 0x00000089} , + {0x0010e06c, 0x0000008A} , + {0x0010e06c, 0x000000A2} , + {0x0010e06c, 0x00000097} , + {0x0010e06c, 0x00000092} , + {0x0010e06c, 0x00000099} , + {0x0010e06c, 0x0000009B} , + {0x0010e06c, 0x0000009D} , + {0x0010e06c, 0x0000009F} , + {0x0010e06c, 0x000000A1} , + {0x0010e06c, 0x00000096} , + {0x0010e06c, 0x00000091} , + {0x0010e06c, 0x00000098} , + {0x0010e06c, 0x0000009A} , + {0x0010e06c, 0x0000009C} , + {0x0010e06c, 0x0000009E} , {0x0010ab14, 0x00000000} , {0x0010e024, 0x00000000} , {0x0010e028, 0x00000000} , {0x0010e11c, 0x00000000} , - {0x0010ab1c, 0x140B0B55} , - {0x0010e020, 0x0E262655} , - {0x0010e124, 0x25101055} , + {0x0010ab1c, 0x140B0BFF} , + {0x0010e020, 0x0E2626FF} , + {0x0010e124, 0x251010FF} , {0x0010ab20, 0x89abcdef} , {0x0010ab24, 0x00000000} , {0x0010e02c, 0x89abcdef} , {0x0010e030, 0x00000000} , {0x0010e128, 0x89abcdef} , {0x0010e12c, 0x00000000} , - {0x0010ab28, 0x75555555} , + {0x0010ab28, 0x7FFFFFFF} , {0x0010ab2c, 0x70000000} , - {0x0010e034, 0x75555555} , + {0x0010e034, 0x7FFFFFFF} , {0x0010e038, 0x70000000} , - {0x0010e130, 0x75555555} , + {0x0010e130, 0x7FFFFFFF} , {0x0010e134, 0x70000000} , {0x0010ab30, 0x00000000} , {0x0010ab34, 0x00000001} , @@ -97,8 +97,8 @@ static struct pg_init_sequence_list _pginitseq_gp10b[] = { {0x0010e05c, 0x00000000} , {0x0010e044, 0x00000000} , {0x0010a644, 0x0000868B} , - {0x0010a648, 0x00000000 } , - {0x0010a64c, 0x00829493 } , + {0x0010a648, 0x00000000} , + {0x0010a64c, 0x00829493} , {0x0010a650, 0x00000000} , {0x0010e000, 0} , {0x0010e068, 0x000000A3} , @@ -111,24 +111,24 @@ static struct pg_init_sequence_list _pginitseq_gp10b[] = { {0x0010e068, 0x00000087} , {0x0010e068, 0x00000088} , {0x0010e068, 0x0000008D} , - {0x0010e068, 0x000000A00} , - {0x0010e068, 0x000000A01} , - {0x0010e068, 0x000000A02} , - {0x0010e068, 0x000000A03} , - {0x0010e068, 0x000000A04} , - {0x0010e068, 0x000000A05} , - {0x0010e068, 0x000000A06} , - {0x0010e068, 0x000000A07} , - {0x0010e068, 0x000000A08} , - {0x0010e068, 0x000000A09} , - {0x0010e068, 0x000000950} , - {0x0010e068, 0x000000951} , - {0x0010e068, 0x000000952} , - {0x0010e068, 0x000000953} , - {0x0010e068, 0x000000954} , - {0x0010e068, 0x000000955} , - {0x0010e068, 0x000000956} , - {0x0010e068, 0x000000957} , + {0x0010e068, 0x00000082} , + {0x0010e068, 0x00000083} , + {0x0010e068, 0x00000089} , + {0x0010e068, 0x0000008A} , + {0x0010e068, 0x000000A2} , + {0x0010e068, 0x00000097} , + {0x0010e068, 0x00000092} , + {0x0010e068, 0x00000099} , + {0x0010e068, 0x0000009B} , + {0x0010e068, 0x0000009D} , + {0x0010e068, 0x0000009F} , + {0x0010e068, 0x000000A1} , + {0x0010e068, 0x00000096} , + {0x0010e068, 0x00000091} , + {0x0010e068, 0x00000098} , + {0x0010e068, 0x0000009A} , + {0x0010e068, 0x0000009C} , + {0x0010e068, 0x0000009E} , {0x0010e000, 0} , {0x0010e004, 0x0000008E}, }; -- cgit v1.2.2 From 4c5bc9c93b86d9de022d6baff343217f1d047a62 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Tue, 8 Dec 2015 15:43:39 -0800 Subject: gpu: nvgpu: gp10b: clean-up pmu init operations Removed unwanted initlization of function pointer. Bug 200157852 Change-Id: I3b44ccce366f1b72c3ff769a7b9ab350bb2c0066 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/843218 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index dc7539a8..00701a50 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B PMU * - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -332,8 +332,6 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; } else { gk20a_init_pmu_ops(gops); - gops->pmu.pmu_setup_hw_and_bootstrap = - gm20b_init_nspmu_setup_hw1; gops->pmu.load_lsfalcon_ucode = NULL; gops->pmu.init_wpr_region = NULL; gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; -- cgit v1.2.2 From 640d0e2c3b58294cd11f420a5fc8377d490c43d3 Mon Sep 17 00:00:00 2001 From: Supriya Date: Thu, 10 Dec 2015 12:54:38 +0530 Subject: gpu: nvgpu: ECC override -sysfs functions to call into LS PMU and modify ECC overide register Bug 1699676 Change-Id: Iaf6cc3a86160b806e52ab168577caad42b2c5d22 Signed-off-by: Supriya Reviewed-on: http://git-master/r/921252 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 76 ++++++++++++++++++++++++++++++++++++- 1 file changed, 75 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 00701a50..6a704813 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -2,7 +2,7 @@ * GP10B PMU * * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. -* + * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. @@ -14,6 +14,7 @@ */ #include /* for udelay */ +#include #include "gk20a/gk20a.h" #include "gk20a/pmu_gk20a.h" #include "gm20b/acr_gm20b.h" @@ -21,6 +22,7 @@ #include "pmu_gp10b.h" #include "hw_pwr_gp10b.h" +#include "gp10b_sysfs.h" #define gp10b_dbg_pmu(fmt, arg...) \ gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) @@ -324,6 +326,76 @@ static int gp10b_init_pmu_setup_hw1(struct gk20a *g) } +static void pmu_handle_ecc_en_dis_msg(struct gk20a *g, struct pmu_msg *msg, + void *param, u32 handle, u32 status) +{ + struct pmu_gk20a *pmu = &g->pmu; + struct pmu_msg_lrf_tex_ltc_dram_en_dis *ecc = + &msg->msg.lrf_tex_ltc_dram.en_dis; + gk20a_dbg_fn(""); + + if (status != 0) { + gk20a_err(dev_from_gk20a(g), "ECC en dis cmd aborted"); + return; + } + if (msg->msg.lrf_tex_ltc_dram.msg_type != + PMU_LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS) { + gk20a_err(dev_from_gk20a(g), + "Invalid msg for LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS cmd"); + return; + } else if (ecc->pmu_status != 0) { + gk20a_err(dev_from_gk20a(g), + "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg status = %x", + ecc->pmu_status); + gk20a_err(dev_from_gk20a(g), + "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg en fail = %x", + ecc->en_fail_mask); + gk20a_err(dev_from_gk20a(g), + "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg dis fail = %x", + ecc->dis_fail_mask); + } else + pmu->override_done = 1; + gk20a_dbg_fn("done"); +} + +static int send_ecc_overide_en_dis_cmd(struct gk20a *g, u32 bitmask) +{ + struct pmu_gk20a *pmu = &g->pmu; + struct pmu_cmd cmd; + u32 seq; + int status; + gk20a_dbg_fn(""); + + if (!tegra_fuse_readl(FUSE_OPT_ECC_EN)) { + gk20a_err(dev_from_gk20a(g), "Board not ECC capable"); + return -1; + } + if (!(g->acr.capabilities & + ACR_LRF_TEX_LTC_DRAM_PRIV_MASK_ENABLE_LS_OVERRIDE)) { + gk20a_err(dev_from_gk20a(g), "check ACR capabilities"); + return -1; + } + memset(&cmd, 0, sizeof(struct pmu_cmd)); + cmd.hdr.unit_id = PMU_UNIT_FECS_MEM_OVERRIDE; + cmd.hdr.size = PMU_CMD_HDR_SIZE + + sizeof(struct pmu_cmd_lrf_tex_ltc_dram_en_dis); + cmd.cmd.lrf_tex_ltc_dram.en_dis.cmd_type = + PMU_LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS; + cmd.cmd.lrf_tex_ltc_dram.en_dis.en_dis_mask = (u8)(bitmask & 0xff); + + gp10b_dbg_pmu("cmd post PMU_ECC_CMD_ID_EN_DIS_ECC"); + pmu->override_done = 0; + status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, + pmu_handle_ecc_en_dis_msg, NULL, &seq, ~0); + if (status) + gk20a_err(dev_from_gk20a(g), "ECC override failed"); + else + pmu_wait_message_cond(pmu, gk20a_get_gr_idle_timeout(g), + &pmu->override_done, 1); + gk20a_dbg_fn("done"); + return status; +} + void gp10b_init_pmu_ops(struct gpu_ops *gops) { if (gops->privsecurity) { @@ -342,4 +414,6 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase; gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics; gops->pmu.pmu_pg_grinit_param = gp10b_pg_gr_init; + gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = + send_ecc_overide_en_dis_cmd; } -- cgit v1.2.2 From 49cedb9650d178ad5653b55885d022aacbd66f61 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 19 May 2016 09:31:14 -0700 Subject: gpu: nvgpu: gp10b: Use gk20a version of PMU reset Change-Id: I9b6c2e3bcae4ac43a20089e05891654654df1b54 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1150541 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 6a704813..fca84116 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -416,4 +416,5 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.pmu_pg_grinit_param = gp10b_pg_gr_init; gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = send_ecc_overide_en_dis_cmd; + gops->pmu.reset = gk20a_pmu_reset; } -- cgit v1.2.2 From a549165e7332c7618a61fbe65b86bf212901fee2 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Mon, 23 May 2016 16:31:45 +0530 Subject: gpu: nvgpu: secure boot HAL update -And also enable GPCCS load using DMA Updated/added secure boot HAL with methods required to support multiple GPU chips. JIRA DNVGPU-10 Change-Id: Id4546fa74954ba7be7c4544d74ad2b7a31b0ecec Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1151788 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 47 +++++++++++++++++++++++++++++++++---- 1 file changed, 43 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index fca84116..ab736fbe 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -156,7 +156,8 @@ static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, cmd.cmd.acr.boot_falcons.flags = flags; cmd.cmd.acr.boot_falcons.falconidmask = falconidmask; - cmd.cmd.acr.boot_falcons.usevamask = 0; + cmd.cmd.acr.boot_falcons.usevamask = + 1 << LSF_FALCON_ID_GPCCS; cmd.cmd.acr.boot_falcons.wprvirtualbase.lo = u64_lo32(g->pmu.wpr_buf.gpu_va); cmd.cmd.acr.boot_falcons.wprvirtualbase.hi = @@ -171,7 +172,7 @@ static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, return; } -static int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) +int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) { u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; @@ -221,7 +222,7 @@ static void pmu_handle_gr_param_msg(struct gk20a *g, struct pmu_msg *msg, return; } -static int gp10b_pg_gr_init(struct gk20a *g, u8 grfeaturemask) +int gp10b_pg_gr_init(struct gk20a *g, u8 grfeaturemask) { struct pmu_gk20a *pmu = &g->pmu; struct pmu_cmd cmd; @@ -280,7 +281,7 @@ static int gp10b_pmu_setup_elpg(struct gk20a *g) return ret; } -static void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr) +void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr) { gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr); @@ -396,12 +397,50 @@ static int send_ecc_overide_en_dis_cmd(struct gk20a *g, u32 bitmask) return status; } +static bool gp10b_is_lazy_bootstrap(u32 falcon_id) +{ + bool enable_status = false; + + switch (falcon_id) { + case LSF_FALCON_ID_FECS: + enable_status = false; + break; + case LSF_FALCON_ID_GPCCS: + enable_status = true; + break; + default: + break; + } + + return enable_status; +} + +static bool gp10b_is_priv_load(u32 falcon_id) +{ + bool enable_status = false; + + switch (falcon_id) { + case LSF_FALCON_ID_FECS: + enable_status = false; + break; + case LSF_FALCON_ID_GPCCS: + enable_status = false; + break; + default: + break; + } + + return enable_status; +} + void gp10b_init_pmu_ops(struct gpu_ops *gops) { if (gops->privsecurity) { gm20b_init_secure_pmu(gops); gops->pmu.init_wpr_region = gm20b_pmu_init_acr; gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; + gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; + gops->pmu.is_priv_load = gp10b_is_priv_load; } else { gk20a_init_pmu_ops(gops); gops->pmu.load_lsfalcon_ucode = NULL; -- cgit v1.2.2 From a334f78461a1d5a840275a3c55d9b5b41eeca699 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 27 May 2016 12:05:59 -0700 Subject: gpu: nvgpu: Force GPCCS priv load Use priv load for GPCCS instead of DMA. Bug 200204675 Change-Id: Ic7ea7d9e0ef98330e0bdd7606284b8fb3c5bfec8 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1155281 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: David Martinez Nieto --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index ab736fbe..7832b2ed 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -156,8 +156,7 @@ static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, cmd.cmd.acr.boot_falcons.flags = flags; cmd.cmd.acr.boot_falcons.falconidmask = falconidmask; - cmd.cmd.acr.boot_falcons.usevamask = - 1 << LSF_FALCON_ID_GPCCS; + cmd.cmd.acr.boot_falcons.usevamask = 0; cmd.cmd.acr.boot_falcons.wprvirtualbase.lo = u64_lo32(g->pmu.wpr_buf.gpu_va); cmd.cmd.acr.boot_falcons.wprvirtualbase.hi = @@ -424,7 +423,7 @@ static bool gp10b_is_priv_load(u32 falcon_id) enable_status = false; break; case LSF_FALCON_ID_GPCCS: - enable_status = false; + enable_status = true; break; default: break; -- cgit v1.2.2 From 4e321eb1c84dca5f045b6ad1363cdc35ab763462 Mon Sep 17 00:00:00 2001 From: Supriya Date: Wed, 23 Mar 2016 20:33:02 +0530 Subject: gpu: nvgpu: Add Fuse prints on PMU Halt -Print fuse values in case of PMU halt error -and mailbox reads 0xDEADDEAD Bug 1737044 Change-Id: Icb9677ca278bd316232e07f1d92980f6deb17125 Signed-off-by: Supriya Reviewed-on: http://git-master/r/1120988 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 7832b2ed..f40c1b7b 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -22,6 +22,7 @@ #include "pmu_gp10b.h" #include "hw_pwr_gp10b.h" +#include "hw_fuse_gp10b.h" #include "gp10b_sysfs.h" #define gp10b_dbg_pmu(fmt, arg...) \ @@ -432,6 +433,17 @@ static bool gp10b_is_priv_load(u32 falcon_id) return enable_status; } +/*Dump Security related fuses*/ +static void pmu_dump_security_fuses_gp10b(struct gk20a *g) +{ + gk20a_err(dev_from_gk20a(g), "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", + gk20a_readl(g, fuse_opt_sec_debug_en_r())); + gk20a_err(dev_from_gk20a(g), "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", + gk20a_readl(g, fuse_opt_priv_sec_en_r())); + gk20a_err(dev_from_gk20a(g), "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", + tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0)); +} + void gp10b_init_pmu_ops(struct gpu_ops *gops) { if (gops->privsecurity) { @@ -455,4 +467,5 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = send_ecc_overide_en_dis_cmd; gops->pmu.reset = gk20a_pmu_reset; + gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gp10b; } -- cgit v1.2.2 From 49840c15efb36b3216357b93ba0477e53dbef3b6 Mon Sep 17 00:00:00 2001 From: Shardar Shariff Md Date: Fri, 9 Sep 2016 02:36:04 +0530 Subject: gpu: nvgpu: change the usage of tegra_fuse_readl tegra_fuse_readl() prototype is changed to match upstreamed fuse driver, so change implementation accordingly. Bug 200233653 Change-Id: Ib690cf8a5a69e7b13146471a5ee211834dc40086 Signed-off-by: Shardar Shariff Md Reviewed-on: http://git-master/r/1217376 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index f40c1b7b..762e2af7 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -365,9 +365,11 @@ static int send_ecc_overide_en_dis_cmd(struct gk20a *g, u32 bitmask) struct pmu_cmd cmd; u32 seq; int status; + u32 val; gk20a_dbg_fn(""); - if (!tegra_fuse_readl(FUSE_OPT_ECC_EN)) { + tegra_fuse_readl(FUSE_OPT_ECC_EN, &val); + if (!val) { gk20a_err(dev_from_gk20a(g), "Board not ECC capable"); return -1; } @@ -436,12 +438,15 @@ static bool gp10b_is_priv_load(u32 falcon_id) /*Dump Security related fuses*/ static void pmu_dump_security_fuses_gp10b(struct gk20a *g) { + u32 val; + gk20a_err(dev_from_gk20a(g), "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", gk20a_readl(g, fuse_opt_sec_debug_en_r())); gk20a_err(dev_from_gk20a(g), "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", gk20a_readl(g, fuse_opt_priv_sec_en_r())); + tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val); gk20a_err(dev_from_gk20a(g), "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", - tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0)); + val); } void gp10b_init_pmu_ops(struct gpu_ops *gops) -- cgit v1.2.2 From 84219f3a7f022e684c83ed9e6414bd9f2827c025 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Thu, 27 Oct 2016 11:09:10 -0700 Subject: gpu: nvgpu: gp10b: pmu HAL update Update pmu HAL to have function for is_pmu_supported. JIRA GV11B-21 Change-Id: Id08efa82aa04a6f92c7fea0eb5d4735db2699b5a Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1243918 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: Alex Waterman Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 762e2af7..e7b2e70c 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -449,8 +449,14 @@ static void pmu_dump_security_fuses_gp10b(struct gk20a *g) val); } +static bool gp10b_is_pmu_supported(struct gk20a *g) +{ + return true; +} + void gp10b_init_pmu_ops(struct gpu_ops *gops) { + gops->pmu.is_pmu_supported = gp10b_is_pmu_supported; if (gops->privsecurity) { gm20b_init_secure_pmu(gops); gops->pmu.init_wpr_region = gm20b_pmu_init_acr; -- cgit v1.2.2 From fd2b0a48605b8019906650e829f45b6260edaae7 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 3 Nov 2016 15:53:54 +0530 Subject: gpu: nvgpu: update pg engine init/list/features HAL - Updated gp10b_pg_gr_init() to post init param based on PG engine parameter - Assigned pg engine list/features HAL to respective functions/NULL JIRA DNVGPU-71 Change-Id: I7d059796746694b22800c6ae0327cbc90331e929 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1247407 (cherry-picked from commit aee4e565ca2b475c0680674e4e6345b3b30cc502) Reviewed-on: http://git-master/r/1269321 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 38 +++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index e7b2e70c..b5fdf2fd 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -222,26 +222,30 @@ static void pmu_handle_gr_param_msg(struct gk20a *g, struct pmu_msg *msg, return; } -int gp10b_pg_gr_init(struct gk20a *g, u8 grfeaturemask) +int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) { struct pmu_gk20a *pmu = &g->pmu; struct pmu_cmd cmd; u32 seq; - memset(&cmd, 0, sizeof(struct pmu_cmd)); - cmd.hdr.unit_id = PMU_UNIT_PG; - cmd.hdr.size = PMU_CMD_HDR_SIZE + - sizeof(struct pmu_pg_cmd_gr_init_param); - cmd.cmd.pg.gr_init_param.cmd_type = - PMU_PG_CMD_ID_PG_PARAM; - cmd.cmd.pg.gr_init_param.sub_cmd_id = - PMU_PG_PARAM_CMD_GR_INIT_PARAM; - cmd.cmd.pg.gr_init_param.featuremask = - grfeaturemask; - - gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM %x", grfeaturemask); - gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, - pmu_handle_gr_param_msg, pmu, &seq, ~0); + if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { + memset(&cmd, 0, sizeof(struct pmu_cmd)); + cmd.hdr.unit_id = PMU_UNIT_PG; + cmd.hdr.size = PMU_CMD_HDR_SIZE + + sizeof(struct pmu_pg_cmd_gr_init_param); + cmd.cmd.pg.gr_init_param.cmd_type = + PMU_PG_CMD_ID_PG_PARAM; + cmd.cmd.pg.gr_init_param.sub_cmd_id = + PMU_PG_PARAM_CMD_GR_INIT_PARAM; + cmd.cmd.pg.gr_init_param.featuremask = + PMU_PG_FEATURE_GR_POWER_GATING_ENABLED; + + gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM "); + gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, + pmu_handle_gr_param_msg, pmu, &seq, ~0); + + } else + return -EINVAL; return 0; } @@ -474,7 +478,9 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.fecsbootstrapdone = false; gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase; gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics; - gops->pmu.pmu_pg_grinit_param = gp10b_pg_gr_init; + gops->pmu.pmu_pg_init_param = gp10b_pg_gr_init; + gops->pmu.pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list; + gops->pmu.pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list; gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = send_ecc_overide_en_dis_cmd; gops->pmu.reset = gk20a_pmu_reset; -- cgit v1.2.2 From 62d13e613807e9bce3a9d1ef0c61725ef3a885ce Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 3 Nov 2016 17:34:12 +0530 Subject: gpu: nvgpu: RPPG support - Added rppg module to init GR/MS-RPPG. mscg is dependent on gr-rppg & without gr-rppg engage mscg does not engage. - Update pg engines HAL to return supported pg engines & its sub features JIRA DNVGPU-71 Change-Id: Ib0fd2d79b509f6f2f1dabae6e2b5aebcc80b5691 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1247486 (cherry picked from commit 86e45fa62e6a6b295f73c0173f0117ae9f78a5e9) Reviewed-on: http://git-master/r/1270762 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index b5fdf2fd..cd9cd0b0 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -249,7 +249,8 @@ int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) return 0; } -static void gp10b_pmu_elpg_statistics(struct gk20a *g, + +void gp10b_pmu_elpg_statistics(struct gk20a *g, u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt) { struct pmu_gk20a *pmu = &g->pmu; -- cgit v1.2.2 From e5824d8014c321fbe2c1e04e12307125dd50a472 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 3 Nov 2016 21:16:21 +0530 Subject: gpu: nvgpu: MSCG support - update gp106 pg engine init/list/features HALs to support MS engine - Added defines & interface for lpwr tables read from vbios. - lpwr module which reads idx/gr/ms table from vbios to map rppg/mscg support with respective p-state - lpwr module public functions to control lpwr features enable/disable mscg/rppg & mclk-change request whenever change in mclk-change parameters - lpwr public functions to know rppg/mscg support for requested pstate, - added mutex t prevent PG transition while arbiter executes pstate transition - nvgpu_clk_arb_get_current_pstate() of clk arbiter to get current pstate JIRA DNVGPU-71 Change-Id: Ifcd640cc19ef630be1e2a9ba07ec84023d8202a0 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1247553 (cherry picked from commit 8a441dea2410e1b5196ef24e56a7768b6980e46b) Reviewed-on: http://git-master/r/1270989 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index cd9cd0b0..9274990a 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -482,6 +482,9 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.pmu_pg_init_param = gp10b_pg_gr_init; gops->pmu.pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list; gops->pmu.pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list; + gops->pmu.pmu_lpwr_enable_pg = NULL; + gops->pmu.pmu_lpwr_disable_pg = NULL; + gops->pmu.pmu_pg_param_post_init = NULL; gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = send_ecc_overide_en_dis_cmd; gops->pmu.reset = gk20a_pmu_reset; -- cgit v1.2.2 From 76a18f5e762c79e8e6902ec93b7d6ea741475365 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 9 Nov 2016 19:33:41 +0530 Subject: gpu: nvgpu: PG statistics update - PG statistics read support for multiple engines JIRA DNVGPU-71 Change-Id: I2dc3aad243300d21dc3d20a54a5e4736977e071b Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1250507 (cherry picked from commit 985cb3be1d6d990bc6651e417d9e6ba9bfe306e0) Reviewed-on: http://git-master/r/1270991 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/pmu_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 9274990a..12337934 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -250,13 +250,14 @@ int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) return 0; } -void gp10b_pmu_elpg_statistics(struct gk20a *g, +void gp10b_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt) { struct pmu_gk20a *pmu = &g->pmu; struct pmu_pg_stats_v1 stats; - pmu_copy_from_dmem(pmu, pmu->stat_dmem_offset, + pmu_copy_from_dmem(pmu, + pmu->stat_dmem_offset[pg_engine_id], (u8 *)&stats, sizeof(struct pmu_pg_stats_v1), 0); *ingating_time = stats.total_sleep_timeus; -- cgit v1.2.2