From 0b50f2a2020c81f00999a8f06a67dde4c214821f Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 27 Oct 2014 15:05:45 +0200 Subject: gpu: nvgpu: Implement gp10b intr processing Bug 1567274 Change-Id: I2a6cef954b56d1f97208d29584e0748ec1c5e29d Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/591628 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 135 +++++++++++++++++++++++++++++++++++++ 1 file changed, 135 insertions(+) create mode 100644 drivers/gpu/nvgpu/gp10b/mc_gp10b.c (limited to 'drivers/gpu/nvgpu/gp10b/mc_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c new file mode 100644 index 00000000..cdafaf56 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -0,0 +1,135 @@ +/* + * GP20B master + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include "gk20a/gk20a.h" +#include "mc_gp10b.h" +#include "hw_mc_gp10b.h" + +void mc_gp10b_intr_enable(struct gk20a *g) +{ + if (!tegra_platform_is_linsim()) { + gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); + gk20a_writel(g, mc_intr_en_set_r(0), + mc_intr_pfifo_pending_f() + | mc_intr_pgraph_pending_f()); + gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); + gk20a_writel(g, mc_intr_en_set_r(1), + mc_intr_pfifo_pending_f() + | mc_intr_pgraph_pending_f() + | mc_intr_priv_ring_pending_f() + | mc_intr_ltc_pending_f() + | mc_intr_pbus_pending_f()); + } +} + +irqreturn_t mc_gp10b_isr_stall(struct gk20a *g) +{ + u32 mc_intr_0; + + if (!g->power_on) + return IRQ_NONE; + + /* not from gpu when sharing irq with others */ + mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); + if (unlikely(!mc_intr_0)) + return IRQ_NONE; + + gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); + + return IRQ_WAKE_THREAD; +} + +irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g) +{ + u32 mc_intr_1; + + if (!g->power_on) + return IRQ_NONE; + + /* not from gpu when sharing irq with others */ + mc_intr_1 = gk20a_readl(g, mc_intr_r(1)); + if (unlikely(!mc_intr_1)) + return IRQ_NONE; + + gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); + + return IRQ_WAKE_THREAD; +} + +irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) +{ + u32 mc_intr_0; + + gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); + + mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); + + gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); + + if (mc_intr_0 & mc_intr_pgraph_pending_f()) + gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); + if (mc_intr_0 & mc_intr_pfifo_pending_f()) + gk20a_fifo_isr(g); + if (mc_intr_0 & mc_intr_pmu_pending_f()) + gk20a_pmu_isr(g); + if (mc_intr_0 & mc_intr_priv_ring_pending_f()) + gk20a_priv_ring_isr(g); + if (mc_intr_0 & mc_intr_ltc_pending_f()) + g->ops.ltc.isr(g); + if (mc_intr_0 & mc_intr_pbus_pending_f()) + gk20a_pbus_isr(g); + + gk20a_writel(g, mc_intr_en_set_r(0), + mc_intr_pfifo_pending_f() + | mc_intr_pgraph_pending_f()); + + return IRQ_HANDLED; +} + +irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) +{ + u32 mc_intr_1; + + gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); + + mc_intr_1 = gk20a_readl(g, mc_intr_r(1)); + + gk20a_dbg(gpu_dbg_intr, "non-stall intr %08x\n", mc_intr_1); + + if (mc_intr_1 & mc_intr_pfifo_pending_f()) + gk20a_fifo_nonstall_isr(g); + if (mc_intr_1 & mc_intr_pgraph_pending_f()) + gk20a_gr_nonstall_isr(g); + + gk20a_writel(g, mc_intr_en_set_r(1), + mc_intr_pfifo_pending_f() + | mc_intr_pgraph_pending_f() + | mc_intr_priv_ring_pending_f() + | mc_intr_ltc_pending_f() + | mc_intr_pbus_pending_f()); + + return IRQ_HANDLED; +} + +void gp10b_init_mc(struct gpu_ops *gops) +{ + gops->mc.intr_enable = mc_gp10b_intr_enable; + gops->mc.isr_stall = mc_gp10b_isr_stall; + gops->mc.isr_nonstall = mc_gp10b_isr_nonstall; + gops->mc.isr_thread_stall = mc_gp10b_intr_thread_stall; + gops->mc.isr_thread_nonstall = mc_gp10b_intr_thread_nonstall; +} -- cgit v1.2.2 From caeddb940fb81b5956939168faf5804cfb3bebfd Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Sat, 1 Nov 2014 19:29:28 +0200 Subject: gpu: nvgpu: gp10b: Enable interrupts in linsim Change-Id: I7d4211743793b905a20080bb44c62c036f23c854 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/592336 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/mc_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index cdafaf56..4f7ab698 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -21,19 +21,17 @@ void mc_gp10b_intr_enable(struct gk20a *g) { - if (!tegra_platform_is_linsim()) { - gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); - gk20a_writel(g, mc_intr_en_set_r(0), - mc_intr_pfifo_pending_f() - | mc_intr_pgraph_pending_f()); - gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); - gk20a_writel(g, mc_intr_en_set_r(1), - mc_intr_pfifo_pending_f() - | mc_intr_pgraph_pending_f() - | mc_intr_priv_ring_pending_f() - | mc_intr_ltc_pending_f() - | mc_intr_pbus_pending_f()); - } + gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); + gk20a_writel(g, mc_intr_en_set_r(0), + mc_intr_pfifo_pending_f() + | mc_intr_pgraph_pending_f()); + gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); + gk20a_writel(g, mc_intr_en_set_r(1), + mc_intr_pfifo_pending_f() + | mc_intr_pgraph_pending_f() + | mc_intr_priv_ring_pending_f() + | mc_intr_ltc_pending_f() + | mc_intr_pbus_pending_f()); } irqreturn_t mc_gp10b_isr_stall(struct gk20a *g) -- cgit v1.2.2 From 2d23236ae26ec6dcbbc934bb372fe56ef839bb80 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 11 Nov 2014 11:13:11 +0200 Subject: gpu: nvgpu: Use queried interrupt ids Change-Id: I258b54447d09b32adc076de50997d792f0567af5 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/601019 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/mc_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 4f7ab698..3fae4ea3 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -21,17 +21,19 @@ void mc_gp10b_intr_enable(struct gk20a *g) { + u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); + gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); gk20a_writel(g, mc_intr_en_set_r(0), mc_intr_pfifo_pending_f() - | mc_intr_pgraph_pending_f()); + | eng_intr_mask); gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); gk20a_writel(g, mc_intr_en_set_r(1), mc_intr_pfifo_pending_f() - | mc_intr_pgraph_pending_f() | mc_intr_priv_ring_pending_f() | mc_intr_ltc_pending_f() - | mc_intr_pbus_pending_f()); + | mc_intr_pbus_pending_f() + | eng_intr_mask); } irqreturn_t mc_gp10b_isr_stall(struct gk20a *g) @@ -71,6 +73,7 @@ irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g) irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) { u32 mc_intr_0; + u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); @@ -78,7 +81,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); - if (mc_intr_0 & mc_intr_pgraph_pending_f()) + if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); if (mc_intr_0 & mc_intr_pfifo_pending_f()) gk20a_fifo_isr(g); @@ -93,7 +96,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) gk20a_writel(g, mc_intr_en_set_r(0), mc_intr_pfifo_pending_f() - | mc_intr_pgraph_pending_f()); + | eng_intr_mask); return IRQ_HANDLED; } @@ -101,6 +104,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) { u32 mc_intr_1; + u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); @@ -110,15 +114,15 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) if (mc_intr_1 & mc_intr_pfifo_pending_f()) gk20a_fifo_nonstall_isr(g); - if (mc_intr_1 & mc_intr_pgraph_pending_f()) + if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) gk20a_gr_nonstall_isr(g); gk20a_writel(g, mc_intr_en_set_r(1), mc_intr_pfifo_pending_f() - | mc_intr_pgraph_pending_f() | mc_intr_priv_ring_pending_f() | mc_intr_ltc_pending_f() - | mc_intr_pbus_pending_f()); + | mc_intr_pbus_pending_f() + | eng_intr_mask); return IRQ_HANDLED; } -- cgit v1.2.2 From d40f3fb2731b9e0586677026dcdeaabf63398933 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Tue, 9 Dec 2014 11:48:54 +0530 Subject: gpu: nvgpu: Handle MC pmu interrupts - Made changes to MC to get pmu interrrupts Change-Id: I07aaec8392b1fbb34ae727bc7547a571aaeeb814 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/661212 Reviewed-by: Bharat Nihalani Tested-by: Bharat Nihalani --- drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 65 +++++++++++++++++++++++++------------- 1 file changed, 43 insertions(+), 22 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/mc_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 3fae4ea3..c7a4bc75 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -23,17 +23,44 @@ void mc_gp10b_intr_enable(struct gk20a *g) { u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); - gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); - gk20a_writel(g, mc_intr_en_set_r(0), - mc_intr_pfifo_pending_f() - | eng_intr_mask); - gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); - gk20a_writel(g, mc_intr_en_set_r(1), - mc_intr_pfifo_pending_f() - | mc_intr_priv_ring_pending_f() - | mc_intr_ltc_pending_f() - | mc_intr_pbus_pending_f() - | eng_intr_mask); + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), + 0xffffffff); + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = + mc_intr_pfifo_pending_f() + | eng_intr_mask; + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); + + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), + 0xffffffff); + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = + mc_intr_pfifo_pending_f() + | mc_intr_priv_ring_pending_f() + | mc_intr_ltc_pending_f() + | mc_intr_pbus_pending_f() + | eng_intr_mask; + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); +} + +void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, + bool is_stalling, u32 mask) +{ + u32 intr_index = 0; + u32 reg = 0; + + intr_index = (is_stalling ? NVGPU_MC_INTR_STALLING : + NVGPU_MC_INTR_NONSTALLING); + if (enable) { + reg = mc_intr_en_set_r(intr_index); + g->ops.mc.intr_mask_restore[intr_index] |= mask; + + } else { + reg = mc_intr_en_clear_r(intr_index); + g->ops.mc.intr_mask_restore[intr_index] &= ~mask; + } + + gk20a_writel(g, reg, mask); } irqreturn_t mc_gp10b_isr_stall(struct gk20a *g) @@ -73,7 +100,6 @@ irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g) irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) { u32 mc_intr_0; - u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); @@ -94,9 +120,8 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) if (mc_intr_0 & mc_intr_pbus_pending_f()) gk20a_pbus_isr(g); - gk20a_writel(g, mc_intr_en_set_r(0), - mc_intr_pfifo_pending_f() - | eng_intr_mask); + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); return IRQ_HANDLED; } @@ -104,7 +129,6 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) { u32 mc_intr_1; - u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); @@ -117,12 +141,8 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) gk20a_gr_nonstall_isr(g); - gk20a_writel(g, mc_intr_en_set_r(1), - mc_intr_pfifo_pending_f() - | mc_intr_priv_ring_pending_f() - | mc_intr_ltc_pending_f() - | mc_intr_pbus_pending_f() - | eng_intr_mask); + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); return IRQ_HANDLED; } @@ -130,6 +150,7 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) void gp10b_init_mc(struct gpu_ops *gops) { gops->mc.intr_enable = mc_gp10b_intr_enable; + gops->mc.intr_unit_config = mc_gp10b_intr_unit_config; gops->mc.isr_stall = mc_gp10b_isr_stall; gops->mc.isr_nonstall = mc_gp10b_isr_nonstall; gops->mc.isr_thread_stall = mc_gp10b_intr_thread_stall; -- cgit v1.2.2 From 08b8c0564866c9a37e1790f603f8f4ebdfe4dbf4 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Wed, 3 Dec 2014 11:20:11 -0800 Subject: gpu: nvgpu: gp10b: enable replayable fault interrupt Bug 1587825 Change-Id: I6df2f870b4488bb3d5ada52b4819f6f80624becd Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/659092 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/gp10b/mc_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index c7a4bc75..1760b6ad 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -1,7 +1,7 @@ /* * GP20B master * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -27,6 +27,7 @@ void mc_gp10b_intr_enable(struct gk20a *g) 0xffffffff); g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = mc_intr_pfifo_pending_f() + | mc_intr_replayable_fault_pending_f() | eng_intr_mask; gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); -- cgit v1.2.2 From 20a1ab078546c7206bb65ab007882195953df1dd Mon Sep 17 00:00:00 2001 From: Sam Payne Date: Thu, 5 Feb 2015 10:46:35 -0800 Subject: gpu: nvgpu: gp10b: add ce interrupt support ce interrupts use different register mapping and format from gk20a and gm20b. Change-Id: Icfe33bad940b2b829b6f57d07a3300adaf53d43c Signed-off-by: Sam Payne Reviewed-on: http://git-master/r/681646 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/gpu/nvgpu/gp10b/mc_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 1760b6ad..47c8fcc6 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -110,6 +110,9 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); + if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) + && g->ops.ce2.isr_stall) + g->ops.ce2.isr_stall(g); if (mc_intr_0 & mc_intr_pfifo_pending_f()) gk20a_fifo_isr(g); if (mc_intr_0 & mc_intr_pmu_pending_f()) @@ -141,6 +144,11 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) gk20a_fifo_nonstall_isr(g); if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) gk20a_gr_nonstall_isr(g); + if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) + && g->ops.ce2.isr_nonstall) + g->ops.ce2.isr_nonstall(g); + + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); -- cgit v1.2.2 From 1f225fa73167ec31c9332e4031c156d8b04a41f6 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 13 May 2016 12:22:21 -0700 Subject: gpu: nvgpu: Implement engine_enum_from_type Implement a helper function engine_enum_from_type. This allows parsing device_info entries for LCE engine type. Pascal has logical copy engine instead of CE2, so so add definition of that. Change-Id: I71f59c308641d84ac59fd57fc37d9b627bb07a43 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1147747 Reviewed-by: Konsta Holtta --- drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/mc_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 47c8fcc6..4d9573d1 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -108,9 +108,9 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); - if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) + if (mc_intr_0 & g->fifo.engine_info[ENGINE_GR_GK20A].intr_mask) gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); - if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) + if (mc_intr_0 & g->fifo.engine_info[ENGINE_CE2_GK20A].intr_mask && g->ops.ce2.isr_stall) g->ops.ce2.isr_stall(g); if (mc_intr_0 & mc_intr_pfifo_pending_f()) @@ -142,9 +142,9 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) if (mc_intr_1 & mc_intr_pfifo_pending_f()) gk20a_fifo_nonstall_isr(g); - if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) + if (mc_intr_1 & g->fifo.engine_info[ENGINE_GR_GK20A].intr_mask) gk20a_gr_nonstall_isr(g); - if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) + if (mc_intr_1 & g->fifo.engine_info[ENGINE_CE2_GK20A].intr_mask && g->ops.ce2.isr_nonstall) g->ops.ce2.isr_nonstall(g); -- cgit v1.2.2 From 9454529abe0ac42d15df01e36898cd2c840de9c8 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Thu, 2 Jun 2016 09:39:52 +0530 Subject: gpu: nvgpu: Add multiple engine and runlist support This CL covers the following modification, 1) Added multiple engine_info support 2) Added multiple runlist_info support 3) Initial changes for ASYNC CE support 4) Added ASYNC CE interrupt support for Pascal GPU series 5) Removed hard coded engine_id logic and made generic way 6) Code cleanup for readability JIRA DNVGPU-26 Change-Id: Ibf46a89a5308c82f01040ffa979c5014b3206f8e Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1156022 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 59 ++++++++++++++++++++++++++++++-------- 1 file changed, 47 insertions(+), 12 deletions(-) (limited to 'drivers/gpu/nvgpu/gp10b/mc_gp10b.c') diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 4d9573d1..eda961b6 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -1,7 +1,7 @@ /* * GP20B master * - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -101,6 +101,9 @@ irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g) irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) { u32 mc_intr_0; + u32 engine_id_idx; + u32 active_engine_id = 0; + u32 engine_enum = ENGINE_INVAL_GK20A; gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); @@ -108,11 +111,26 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); - if (mc_intr_0 & g->fifo.engine_info[ENGINE_GR_GK20A].intr_mask) - gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); - if (mc_intr_0 & g->fifo.engine_info[ENGINE_CE2_GK20A].intr_mask - && g->ops.ce2.isr_stall) - g->ops.ce2.isr_stall(g); + for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { + active_engine_id = g->fifo.active_engines_list[engine_id_idx]; + + if (mc_intr_0 & g->fifo.engine_info[active_engine_id].intr_mask) { + engine_enum = g->fifo.engine_info[active_engine_id].engine_enum; + /* GR Engine */ + if (engine_enum == ENGINE_GR_GK20A) { + gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); + } + + /* CE Engine */ + if (((engine_enum == ENGINE_GRCE_GK20A) || + (engine_enum == ENGINE_ASYNC_CE_GK20A)) && + g->ops.ce2.isr_stall){ + g->ops.ce2.isr_stall(g, + g->fifo.engine_info[active_engine_id].inst_id, + g->fifo.engine_info[active_engine_id].pri_base); + } + } + } if (mc_intr_0 & mc_intr_pfifo_pending_f()) gk20a_fifo_isr(g); if (mc_intr_0 & mc_intr_pmu_pending_f()) @@ -133,6 +151,9 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) { u32 mc_intr_1; + u32 engine_id_idx; + u32 active_engine_id = 0; + u32 engine_enum = ENGINE_INVAL_GK20A; gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); @@ -142,13 +163,27 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) if (mc_intr_1 & mc_intr_pfifo_pending_f()) gk20a_fifo_nonstall_isr(g); - if (mc_intr_1 & g->fifo.engine_info[ENGINE_GR_GK20A].intr_mask) - gk20a_gr_nonstall_isr(g); - if (mc_intr_1 & g->fifo.engine_info[ENGINE_CE2_GK20A].intr_mask - && g->ops.ce2.isr_nonstall) - g->ops.ce2.isr_nonstall(g); - + for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { + active_engine_id = g->fifo.active_engines_list[engine_id_idx]; + + if (mc_intr_1 & g->fifo.engine_info[active_engine_id].intr_mask) { + engine_enum = g->fifo.engine_info[active_engine_id].engine_enum; + /* GR Engine */ + if (engine_enum == ENGINE_GR_GK20A) { + gk20a_gr_nonstall_isr(g); + } + + /* CE Engine */ + if (((engine_enum == ENGINE_GRCE_GK20A) || + (engine_enum == ENGINE_ASYNC_CE_GK20A)) && + g->ops.ce2.isr_nonstall) { + g->ops.ce2.isr_nonstall(g, + g->fifo.engine_info[active_engine_id].inst_id, + g->fifo.engine_info[active_engine_id].pri_base); + } + } + } gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); -- cgit v1.2.2